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Browse Prior Art Database

Parallel Long Move Instruction

IP.com Disclosure Number: IPCOM000119801D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 89K

Publishing Venue

IBM

Related People

Antognini, J: AUTHOR [+5]

Abstract

Disclosed is a method for processing long move instructions in parallel with subsequent instructions, in such a fashion that any such subsequent instruction waits if necessary so that the machine state after the completion of long move instructions and subsequent instructions executing in parallel is equivalent to that obtained by executing all instructions sequentially.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Parallel Long Move Instruction

      Disclosed is a method for processing long move
instructions in parallel with subsequent instructions, in such a
fashion that any such subsequent instruction waits if necessary so
that the machine state after the completion of long move instructions
and subsequent instructions executing in parallel is equivalent to
that obtained by executing all instructions sequentially.

      Several processor families have a long move instruction of the
general form "MOVE SRC, DST, LNTH", which specifies that LNTH words
are to be moved from the address given by SRC (source) to the address
given by DST (destination), and where "word" refers to the unit of
addressing, e.g., a byte in byte-addressable architectures.  In
pseudo-code this is equivalent to:
           FOR i := 1 TO LNTH DO
                   x := contents at address SRC
                   store x at address DST
                   SRC := SRC+1
                   DST := DST+1.

      We now describe in general terms a method for processing such
long move instructions in parallel with subsequent instructions.
This description can be mapped to various specific processor
architectures and specific processor implementations in a variety of
straightforward ways.  When a long move is encountered in the
instruction stream, this instruction is processed in parallel with
subsequent instructions by a long move instruction unit (LMIU).  This
unit is initialized by setting four registers: SRC, SRC.END, DST, and
DST.END.  SRC and DST are set as specified in the instruction,
SRC.END is set to SRC+LNTH-1, and DST.END is set to DST+LNTH-1.  The
LMIU repeatedly transfers words from the addresses given by the SRC
and DST registers and then increments both registers (as indicated by
the pseudo-code above), until the last transfer takes place when SRC
=  SRC.END.  Note: in the case of a cache this can be designed so
that lines from the source are not brought into the cache and
destination lines are not stored in the cache (but are marked as
invalid if they are in the cache).

      Meanwhile the instruction unit continues processing subsequent
instructions.  For each instruction that generates a memory
reference, the following check is performed, where ADDR is the memory
...