Browse Prior Art Database

SCSI Synchronous Transfer Granularity

IP.com Disclosure Number: IPCOM000119814D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 4 page(s) / 125K

Publishing Venue

IBM

Related People

Cleveland, LD: AUTHOR [+2]

Abstract

A method for achieving increased SCSI Synchronous Transfer rate granularity is disclosed. This characteristic allows a SCSI initiator to attach a variety of targets with widely varying transfer rates, while allowing each to operate at or near its respective potential. A higher performance SCSI system results.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

SCSI Synchronous Transfer Granularity

      A method for achieving increased SCSI Synchronous
Transfer rate granularity is disclosed.  This characteristic allows a
SCSI initiator to attach a variety of targets with widely varying
transfer rates, while allowing each to operate at or near its
respective potential.  A higher performance SCSI system results.

      The SCSI Initiator described is a part of an IOP (I/O
Processor).  The IOP clock period is typically the limiting factor in
establishing the granularity of the available transfer rates from the
SCSI IOP.  It is not possible to choose a clock frequency that is a
multiple of all potential SCSI device synchronous transfer rates, and
at the same time is optimal for all chips on the IOP.

      The 4 phases of the IOP LSSD (Level-Sensitive Scan Design)
clock are utilized to obtain 4 times the granularity available from
the clock period alone.  Since 200 ns is the architected upper limit
for regular SCSI synchronous transfers, it is desirable to have as
many incremental values available from a SCSI initiator as possible
starting at 200 ns and going down to 400 ns.  Below 400 ns the SCSI
targets will likely be running in the asynchronous transfer mode. New
SCSI initiators must be capable of 200 ns transfer rates to match
available rates of peak performing DASD.  The following is an example
of attaching a 250 ns DASD device.

      Fig. 1 illustrates the timing for the 260 ns transfer rate
during a SCSI data out phase.  Signals c1 and c3 are the IOP C and
B LSSD clocks, respectively, while c2 and c4 are the clock phases
separating them.  Signals ctr0 through ctr6 are stages in a Johnson
counter.  Since a 260 ns transfer period is desired and the system
clock is 80 ns, the lowest common denominator of these times is 13/4.
That is 13 IOP clock cycles for each 4 SCSI ACK pulses.  A Johnson
(Ring) counter is chosen since it is simple to implement and decode.
The counter must be capable of being stopped after each SCSI ACK if
the IOP is not ready to provide a byte of data to the SCSI bus
for DATA OUT phase or there are no outstanding SCSI REQUESTS from the
TARGET device (DASD in this case).  The SCSI ACK pulses must be as
close as logic skews will allow to 260 ns from leading edge to
leading edge and not go below the 250 ns which is the DASD minimum
transfer period.  Current CMOS technologies provide this capability.
The ACK pulses mus...