Browse Prior Art Database

Single Point Control for Multiple Subsystems

IP.com Disclosure Number: IPCOM000119824D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 84K

Publishing Venue

IBM

Related People

Bealkowski, R: AUTHOR [+2]

Abstract

This article describes a technique for use in a computer system which provides address decode and recognition switching capability in a shared address register net that allows address range switching without the need to completely re-program the adapters. (Image Omitted)

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Single Point Control for Multiple Subsystems

      This article describes a technique for use in a computer
system which provides address decode and recognition switching
capability in a shared address register net that allows address range
switching without the need to completely re-program the adapters.

                            (Image Omitted)

      In some personal computer systems it is possible to install
feature cards in the system.  Identical feature cards installed in
the same system must be configured to reside at separate address
spaces for both memory and I/O in order to avoid conflicts.  At any
one time, only one card can reside in the "compatible" address space
while all others must be set to alternate addresses.  For software
compatibility the subsystem must reside in the standard spaces in
order to be recognized and programmed.  For example, a system with
four equivalent video cards can have at most one card residing in the
compatible address space. A mechanism is required to dynamically
position a selected member of a subsystem family into the compatible
address space while positioning all others into a set of alternate
address spaces.

      The single point control method (SPCM) for multiple subsystems,
disclosed herein, allows a single architected means for dynamic
reconfiguration.  A control register which is recognized by all
members of a subsystem family is used to provide the selection
mechanism.  Each card must maintain a copy of the control register.
All cards are required to recognize a write operation to the control
register, but only the card currently marked in the "base" (that is,
compatible) address range is to respond to a read operation of the
control register.  In a design where no read-back capability is
required, each card need only recognize the I/O write operation and
respond accordingly.

      It is the control...