Browse Prior Art Database

Pulse-Set, Read-Clear, Register Circuit

IP.com Disclosure Number: IPCOM000119826D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 96K

Publishing Venue

IBM

Related People

Keener, DS: AUTHOR [+2]

Abstract

This article describes a register circuit that will capture an asynchronous event which can later be read and cleared by a processor. This register circuit is automatically reset when it is read. It allows independent reading and clearing of status bits on a per port basis with a single read cycle.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Pulse-Set, Read-Clear, Register Circuit

      This article describes a register circuit that will
capture an asynchronous event which can later be read and cleared by
a processor.  This register circuit is automatically reset when it is
read.  It allows independent reading and clearing of status bits on a
per port basis with a single read cycle.

      When an event occurs at the same time that the register circuit
is read, the automatic "Read-Reset" operation must not prevent the
event from being recorded.  If the bit is read as "set" (or a "1"
state), then it must be reset so that it will not be erroneously read
twice.  The register circuit must work regardless of the time
relationship between the event and the read cycle, and must never
allow an event to be missed or read twice.  This results in one of
two scenarios as follows:
1.   If the event is not passed on to the data bus, it must be
latched by the "Pulse-Set" register circuit.  It must not be affected
by the automatic reset action that occurs when the register circuit
is read.  If it were, this would result in the event being missed by
the processor.
2.   If the event is passed on to the data bus during the current
read cycle, the processor will see it and act accordingly.  In this
case, the event must not be latched, or else on a subsequent read the
processor would see the event again, even though it had occurred only
once.

      The register circuit disclosed herein is automatically reset
when the register is read.  The register only records that an event
happened; it does not count events.  Registers are typically
implemented in eight bits, so eight of these one-bit Pulse-Set
register circuits will be read simultaneously.

      The regis...