Browse Prior Art Database

Three-Stage Decoder With Integrated Clock And Redundancy Control for High-Performance And High-Density CMOS Memories

IP.com Disclosure Number: IPCOM000119836D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 76K

Publishing Venue

IBM

Related People

Katayama, Y: AUTHOR [+3]

Abstract

Disclosed is a circuit for high-speed decoding by passing address information that has been predecoded with the clock (PY) to the post-column-decoder stage in parallel with the main decoding. The redundancy control signal is combined with the predecoded clock (PYAi) by a transmission gate, and the post-decoder for both normal and redundancy is decoded by a single-NMOS-device transmission gate with one small PFET load.

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This is the abbreviated version, containing approximately 54% of the total text.

Three-Stage Decoder With Integrated Clock And Redundancy Control
for High-Performance And High-Density CMOS Memories

      Disclosed is  a circuit for high-speed decoding by
passing address information that has been predecoded with the clock
(PY) to  the post-column-decoder stage in parallel with the main
decoding.  The redundancy control signal is combined with the
predecoded clock (PYAi) by a transmission gate, and the post-decoder
for both normal and redundancy is decoded by a single-NMOS-device
transmission gate with one small PFET load.

      Fig. 1 shows the circuit for this invention.  The decoding path
is the predecoding stage for  both normal and redundancy, the main
decoding stage, in which the main decoder operates in parallel with
the mixing decoder of the pre-decoded clock (PYAi) and the redundancy
control signal (RB), using the transmission gate, and the
post-decoding stage with a single-device transmission gate.  In the
first stage, the necessary address pre-decoding for NB, redundancy
decoding for RB, and clock decoding for PYAi are done in parallel to
avoid any delay. In the second stage, the main decoding circuit is
activated in parallel with the mixing circuit to combine the
redundancy control signal (RB) and the decoded clock (PYAi) by means
of a transmission gate. Finally, the post-single-device transmission
gate with one PMOS pull-up device for either normal (Yi) or
redundancy (RYi)  is activated by gating PAi or PYAi, respectively.
It...