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Static Redundancy Match Detection for High-Speed And Low-Power CMOS Dynamic Memories

IP.com Disclosure Number: IPCOM000119838D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Katayama, T: AUTHOR [+3]

Abstract

Disclosed is a circuit for static redundancy match detection in DRAM address circuits. The static redundancy decoder circuit uses an asymmetric NAND. This circuit needs only one fuse per programmable bit, due to the use of a transmission gate.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 63% of the total text.

Static Redundancy Match Detection for High-Speed And Low-Power CMOS
Dynamic Memories

      Disclosed is a circuit for static redundancy match
detection in DRAM address circuits.   The static redundancy decoder
circuit uses an asymmetric NAND.  This circuit needs only one fuse
per programmable bit, due to the use of a transmission gate.

      Fig. 1 shows the invented circuit for  the static redundancy
match detection.   In the circuit  blocks 1-a and 1-b contain the
fuses.  Levels ACXF, ACXFI,  SETF,  and SETFI are set and maintain
their levels once a negative-going short-pulse  FPU is applied at the
initialization stage.  If a fuse-a or fuse-b is present, ACXF or SETF
is low and ACXFI  or  SETFI is high, respectively.  If a fuse is
blown, ACXF or SETF stays high and ACXFI or SETFI stays low.  The
levels are maintained due to the latching action of the inverter and
PMOS combination, even when there is slight leakage through the blown
fuse.

      In the circuit of the programming-fuse for each address in Fig.
1-a, either an ACXC or an ACXT signal is transmitted to the
asymmetric NAND through the transmission gate and ACXI, depending on
whether fuse-a is present. Fuse-b in the set-fuse section is used to
enable or disable the array select (AS) signal to go to Tn1 NFET
through SET.  SET is enabled when fuse-b is blown.  The Tn1 NFET
device is shared by all the asymmetric NANDs so as to save space. The
sharing of the large NFET gives a better per...