Browse Prior Art Database

Enhanced Switching Controlled NOR Decoder Circuit

IP.com Disclosure Number: IPCOM000119844D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 78K

Publishing Venue

IBM

Related People

Bredin, F: AUTHOR [+3]

Abstract

This decoder aims to provide a NOR logical function from two inputs to "n" inputs without degrading performance. It is a dynamic NOR decoder circuit, and it is suitable to any growable array concept.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 66% of the total text.

Enhanced Switching Controlled NOR Decoder Circuit

      This decoder aims to provide a NOR logical function from
two inputs to "n" inputs without degrading performance.  It is a
dynamic NOR decoder circuit, and it is suitable to any growable array
concept.

      As shown in Fig. 1, in the present implementation of the NOR
decoder circuit, all P devices are suppressed.  The decode function
is accomplished by the NORing of N devices together. The NOR is
precharged to a potential roughly equivalent to a threshold voltage
Vt of N device (TN04), and it is triggered by a pulsed signal
(SSABS).

      Operation of the circuit is given below in conjunction with
Figs.  2 and 3 which illustrate the signal waveforms in the case of
wrong selection.

      In the case of wrong selection, the NOR personnalization does
not match with the T/C address word: TP03/TP06, TN01 and/or TN02 are
ON. N1 and N2 nodes are tied up to VDD level, and VGSL node is
held at VDD-Vt through TN01 and/or TN02 and TN04.  The BIT SWITCH
output (BS) is held at high level.  SSABS signal going low frees TP03
and TP06 and grounds N1 and VGSL nodes through TN03. TN04 and TP04,
respectively, switch OFF and ON. N2 node was previously held at VDD
and remains at this level.  The BS output node also remains at VDD
(Fig. 2).

      In the case of good selection, the NOR logical function is
accomplished.  TN01 and TN02 are OFF. TP03 and TP06 are ON, and the
BIT SWITCH output is held at high level...