Browse Prior Art Database

Overflow Checker Description

IP.com Disclosure Number: IPCOM000119846D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Akrout, C: AUTHOR [+4]

Abstract

The main goal of the novel overflow checker circuit is to provide a "FLAG ERROR" to the user to report a miss addressing within the decoder range.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 62% of the total text.

Overflow Checker Description

      The main goal of the novel overflow checker circuit is to
provide a "FLAG ERROR" to the user to report a miss addressing within
the decoder range.

      For different reasons, ARRAY macros are not completely
addressed and, specifically, when a growable concept is implemented.
The wrong addresses are not always correctly controled by the user.
The idea is to give a "FLAG ERROR" when one of these wrong addresses
is used. The circuit may be connected to any main address bus of a
micro-processor and each time the address word doesn't match with the
address decoder, an overflow positive pulse error is generated that
will remain stored as long as the array macro is miss-addressed.

      Basically, the overflow checker circuit is built up with three
base circuits (Fig. 1).
   1. The Falling Bit Line Checker (FBLC).  It is controlled by the
dummy word line (DWL). When DWL goes high, the dummy bit line goes
low; as a result, the Falling Bit Line Checker circuit generates a
negative pulse (SETBL).
   2. The Up Word Line Checker (UWLC).  All active word lines
exercice this circuit with one exception: the word line DWL. When
obtained, the Up Word Line Checker generates a negative pulse (N3)
any time a word line is selected.
   3. The Overflow Set/Reset Latch (OS/RL).  It has transistors
(TN07/TN08), and reset (TN05/TN06) that are gated by N3 and SETBL
signals. The overflow checker signal is driven by inverter TN11/TP11.

    ...