Browse Prior Art Database

Process-Centering Interlock Circuit

IP.com Disclosure Number: IPCOM000119851D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Bredin, F: AUTHOR [+4]

Abstract

The disclosed process interlock circuit aims to provide the user with a feedback loop servitude system suitable to any ARRAY configuration. It also reduces the maximum current peak during the active cycle.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 93% of the total text.

Process-Centering Interlock Circuit

      The disclosed process interlock circuit aims to provide
the user with a feedback loop servitude system suitable to any ARRAY
configuration.  It also reduces the maximum current peak during the
active cycle.

      Fig. 1 shows the electrical schematic of the present circuit.

      A Dummy Word Line (DWL) and a Dummy Bit Line (DBL) are provided
to trigger the circuit. The DWL is a function of the bit number, and
the DBL is a function of the word line number.

      Selecting the WORD ADDRESS will also activate the DWL. The DWL
drives the DBL. When the desired threshold is reached, the sensing
element (TP03) flips the latch to acknowledge any lowering Bit Line.

      The latch activates the NAND through the reset device (TP07).
The output of the NAND is applied to a standard CMOS buffer (SSA2,
SSABS) and an hysteresis buffer (SSA1).

      The hysteresis element (TN10) is source-gated by the DWL, and
it sequences the output waveforms (see Fig. 2).

      During the active cycle the DWL is high, the latch output is
high (SETBL), and the NAND output is low (N2). In restore mode, when
SETBL switches low, N2 goes high, SSA2 and SSABS switch to high level
and SSA1 remains low as long as DWL stays high.

      SSA1 output going high resets the latch through TN03.

      The advantages of the process interlock circuit are:
1. Complete feedback loop (Dummy Word Line / Dummy Bit Line).
2. Tracking with pr...