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Three-Cycle Pipeline for High Performance SRAM Macros

IP.com Disclosure Number: IPCOM000119853D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 76K

Publishing Venue

IBM

Related People

Akrout, C: AUTHOR [+4]

Abstract

This article describes a specific pipeline used to perform a high speed cycle time of a RAM macro. The access time of this RAM is bigger than the cycle time, and the pipeline is achieved in three stages. When the cycle time becomes smaller than the access time, it is difficult to catch the output data because, depending on the process conditions, the output data could come before the second cycle or after. Fig. 1 shows the data available before the second cycle for the fast conditions and the data available after the second cycle for the slow conditions. The idea is to wait for the third cycle to catch these output data which are valid only within a narrow window around the rising edge of the clock (Fig. 2).

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Three-Cycle Pipeline for High Performance SRAM Macros

      This article describes a specific pipeline used to
perform a high speed cycle time of a RAM macro. The access time of
this RAM is bigger than the cycle time, and the pipeline is achieved
in three stages. When the cycle time becomes smaller than the access
time, it is difficult to catch the output data because, depending on
the process conditions, the output data could come before the second
cycle or after. Fig. 1 shows the data available before the second
cycle for the fast conditions and the data available after the second
cycle for the slow conditions. The idea is to wait for the third
cycle to catch these output data which are valid only within a narrow
window around the rising edge of the clock (Fig. 2).

      Specific circuits, which have good tracking with the internal
timing of the RAM macro, like the Set Word decoder signal or the Set
Sense Amplifier signal, produce a strobe signal from the RAM clock
rising edge. This strobe signal allows the internal data to be caught
in output latches and stored until the next cycle (Figs. 2 and 3).

      Therefore, the slow conditions, on the one hand, determine the
window opening, and the fast conditions close the window when the
output data are available around the RAM clock rising edge.

      This scheme allows a memory product to run with higher
frequency than the frequency a classical pipeline could offer.

      The narrow window of the avail...