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Super-Fast Memory Test for the High Performance Computer

IP.com Disclosure Number: IPCOM000119855D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 90K

Publishing Venue

IBM

Related People

Cheng, C: AUTHOR [+3]

Abstract

Disclosed is a method for an efficient memory test in a high-performance computer that has fault-tolerant features, such as bit-steering and extent-swapping capabilities. The implementation achieves a high level of memory reliability and at the same time substantially shortens the time required for memory testing.

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This is the abbreviated version, containing approximately 52% of the total text.

Super-Fast Memory Test for the High Performance Computer

      Disclosed is a method for an efficient memory test in a
high-performance computer that has fault-tolerant features, such as
bit-steering and extent-swapping capabilities. The implementation
achieves a high level of memory reliability and at the same time
substantially shortens the time required for memory testing.

      Referring to the figure, a computer system includes a central
processor 12 and main memory 14. A cache subsystem 16 is located
between the central processor 12 and the main memory 14. Data and
address lines connect the central processor 12 to the cache 16, and
connect the cache 16 to the main memory 14. In special circumstances,
data lines 18 and address lines 20 can be used to bypass the cache 16
and give the central processor 12 direct access to main memory 14.
The remainder of the system, including mass storage and input/output
devices, is conventional and is not shown in the figure.

      Bit-steering circuitry is part of the processor in some modern
high-performance computers. It allows spare bit(s) to be used as the
replacement bit(s) when fault bits are found. Therefore, a computer
that has such a capability will not suffer a performance loss in case
the bad bit can be replaced by the spare bit using bit steering. In
order to both fully utilize the bit steering capability and maximize
the memory utilization, the memory checking software must check the
entire specified memory area. Recording fault bit address and
location could be a problem when a large number of bit failures are
found. Depending on the number of bad bits found, the number of
general-purpose registers and/or other existing registers, the
machine may or may not be able to keep track of all fault bit
locations. As a result, the bit to steer (based upon the contents of
those registers) may not be the most desirable bit to steer
throughout the entire specified area.

      To implement this memory test, first check out a small portion
of the memory by applying test patterns at randomly selected memory
addresses, do bit steering if possible when an error is detected, and
then check out the rest of the memory area without doing further bit
steering.

      The method described in this article...