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High Performance Logic Circuit With PNP Pull-Up

IP.com Disclosure Number: IPCOM000119859D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Montegari, F: AUTHOR

Abstract

The high-performance logic circuit with PNP pull-up, depicted in the figure, functions as inverting, two-way emitter-coupled logic. Since no load resistors are used, transistor clamps define the up and down signal levels based on two reference voltages, REF1 and REF2, that are preferably generated on chip and temperature compensated.

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High Performance Logic Circuit With PNP Pull-Up

      The high-performance logic circuit with PNP pull-up,
depicted in the figure, functions as inverting, two-way
emitter-coupled logic.  Since no load resistors are used, transistor
clamps define the up and down signal levels based on two reference
voltages, REF1 and REF2, that are preferably generated on chip and
temperature compensated.

      Transistors T1 and T2 provide the logical OR inputs of an NPN
ECL circuit consisting of T1, T2 and common base reference transistor
T3, whose base is connected to reference voltage REF 3.  Their
emitters are connected together and to current source resistor R1
which connects to VEE .  The collectors of T1 and T2 are dotted
together and connected to the output to provide down-level drive to
the loads.  The collector of T3 pulls current from diode-connected
PNP transistor T5 which mirrors its current into PNP transistor T4.
The collector of T4 is connected to the output node and provides
up-level drive to the loads. The base of NPN emitter follower clamp
transistor T6 connects to reference voltage REF 1 which determines
the down level at the output node, and the base of PNP emitter
follower clamp transistor T7 connects to reference voltage REF 2
which determines the up level.

      When input 1 or 2 or both 1 and 2 are at an up
level, T1 or T2 or both T1 and T2 are on and T3 is off.
With T3 off, no current flows in T5, and therefore no current is
mirrored into T4 and T...