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Low Temperature Formation of Source/Drain Junctions Using Selective Amorphous Silicon And Solid Phase Epitaxy

IP.com Disclosure Number: IPCOM000119863D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 100K

Publishing Venue

IBM

Related People

Gambino, JP: AUTHOR [+4]

Abstract

In conventional Si field-effect transistor (FET) processing, source/ drain junctions are formed by ion implantation followed by annealing. The anneal must be at a high-enough temperature (typically 900@C) to remove implant damage. There are a number of problems with this approach: 1. It is difficult to form shallow p-type diffusions, due to deep penetration of implanted B. 2. In pFETs with B-doped gates, B can penetrate thin gate oxides (35 Ao) during anneals at 900@C and above. 3. In most BICMOS processes, the emitter for the bipolar transistors and the source/drains for the FETs share the same drive-in temperature. At a given temperature, the source/ drains require a longer anneal time than the emitters.

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Low Temperature Formation of Source/Drain Junctions Using Selective
Amorphous Silicon And Solid Phase Epitaxy

      In conventional Si field-effect transistor (FET)
processing, source/ drain junctions are formed by ion implantation
followed by annealing.  The anneal must be at a high-enough
temperature (typically 900@C) to remove implant damage. There are a
number of problems with this approach:
      1.   It is difficult to form shallow p-type diffusions, due to
deep penetration of implanted B.
      2.   In pFETs with B-doped gates, B can penetrate thin gate
oxides (35 Ao) during anneals at 900@C and above.
      3.   In most BICMOS processes, the emitter for the bipolar
transistors and the source/drains for the FETs share the same
drive-in temperature.  At a given temperature, the source/ drains
require a longer anneal time than the emitters.  Therefore, the
emitters in a BICMOS process are deeper than those obtained with a
bipolar only process.

      To avoid the above problems, a low temperature process for
fabricating source/drain junctions is proposed.

      The selective deposition of n-type microcrystalline Si (:H:F)
films by RF plasma enhanced chemical vapor deposition (PECVD) has
recently been reported (*).  These films were deposited from a
reactive gas mixture of SiF4 and 100 ppm PH3 in SiH4 at low substrate
temperatures (below 400~C). Films with a conductivity up to 100
(ohm-cm)-1 were obtained, and the process was shown to be 100%
selective. Deposition occurred only on c-Si and poly-Si surfaces and
no deposition was observed in the SiOx regions.  By lowering the
substrate temperature and RF power density, and changing the partial
pressures of SiH4 and SiF4, it should be possible to obtain n-type
amorphous Si :H:F film with the same high selectivity.  This n-type
material would maintain the high selectivity and the low deposition
temperature of the n-type microcrystalline Si :H:F material.  We
propose using selective deposition of in-situ doped amorphous silicon
and low temperature recrystallization to form source and drain
regions in FET...