Browse Prior Art Database

Coherency Requirements of a Single Cache MP System

IP.com Disclosure Number: IPCOM000119864D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 80K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+6]

Abstract

There are several trends in high-end processor design that might allow one to consider new ways of handling cache coherency. These trends involve an increase in the number of tightly coupled processors in an MP configuration and an increase in the sizes of the caches in the memory hierarchy. The question before us is how caches and processors should interact in such an environment and the surprising statement that concurrency can substitute for coherency.

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Coherency Requirements of a Single Cache MP System

      There are several trends in high-end processor design
that might allow one to consider new ways of handling cache
coherency. These trends involve an increase in the number of tightly
coupled processors in an MP configuration and an increase in the
sizes of the caches in the memory hierarchy. The question before us
is how caches and processors should interact in such an environment
and the surprising statement that concurrency can substitute for
coherency.

      COHERENCY IN MP SYSTEMS

      If multiple processors share a single L1-cache which is big
enough to contain the working sets of all the processes running on
the different processors and sufficient cache bandwidth is provided,
then the sole problem that remains to be solved is to provide this
cache with a short access time in such a situation.

      The necessity of adding additional coherency controls in the
case of a single common cache is dependent on the processor
organization.  For organizations that permit out-of-sequence fetching
but do not allow fetches to bypass stores, the disclosed approach is
adequate.

      The terminology that is used to describe out-of-sequence is
that fetching can occur out of sequence from the perspective of the
cache when a fetch is delayed and a subsequent fetch can occur. The
delay on the fetch can result from an AGI, from OSC, or from a cache
miss. In this context a fetch can be said to go out-of-sequence with
respect to a store in the same set of circumstances.  The statement
that a processor allows fetching out-of-sequence but does not allow a
fetch to bypass a preceding store, i.e., when that store has caused a
miss or can not generate its address because of an AGI, now has
precise meaning.

      Coherency in a multiprocessor system involves both the
coherency maintained by the cache and the coherency associated with
the OSC hazard within the pipeline. For a single processor per cache
these...