Browse Prior Art Database

Data Integrity Methodology

IP.com Disclosure Number: IPCOM000119865D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Aichelmann Jr, FJ: AUTHOR [+2]

Abstract

A technique is proposed to maintain data integrity in an L1/L2 latch pair when each half contains unique data.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 62% of the total text.

Data Integrity Methodology

      A technique is proposed to maintain data integrity in an
L1/L2 latch pair when each half contains unique data.

      Present usage of L1/L2 pairs (double buffered two outputs)
(Fig.  1) when "scanned out" in the "normal" fashion, i.e., "A"
clock/"B" clock (or "B" clock/"A" clock) causes the data in one half
to be overwritten by the previous buffer's data in the scan path at
scan start. Thus, in a string of these latch pairs containing unique
data in each half, "normal" scanning will destroy half the data,
causing loss of diagnostic capability.  In addition, this effect is
present when attempting to load unique data via the scan path.

      Unique data may be maintained in these double buffered shift
register latches (SRLs) by combining them with non-buffered (i.e.,
single output SRLs) (Fig. 1) in an alternate fashion within a single
scan ring (Fig. 2).  Other scan ring(s) will contain the remaining
non-buffered SRLs not required to balance the double buffered SRLs.

      The scan clock sequence (for Fig. 2) is as follows:
      Scan "L2"'s
           B'clock - loads "L2"A1 into L2A2 and
                           "L2"B1 into L2B2,
                           etc. "L2"'s into L2's
           A'clock - loads "Scan in" into "L2"A1 and
                           L2A2 into "L2"B1,
                      ...