Browse Prior Art Database

Asynchronous Cache Misses for Closely Shared Data

IP.com Disclosure Number: IPCOM000119866D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 116K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

There are several trends in high-end processor design that might allow one to consider new ways of handling cache misses. These trends involve an increase in the number of tightly coupled processors in an MP configuration that is to represent a single image and an increase in the sizes of the caches in the memory hierarchy. Thus the major source of a cache miss in a memory hierarchy, at the L2-level, say, is the CROSS- INVALIDATES (XI) from the processor associated with the other L2 caches in the system. The concern that will be addressed here is the alternate way of handling cache misses when the contention between processes involves data that is closely shared.

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Asynchronous Cache Misses for Closely Shared Data

      There are several trends in high-end processor design
that might allow one to consider new ways of handling cache misses.
These trends involve an increase in the number of tightly coupled
processors in an MP configuration that is to represent a single image
and an increase in the sizes of the caches in the memory hierarchy.
Thus the major source of a cache miss in a memory hierarchy, at the
L2-level, say, is the CROSS- INVALIDATES (XI) from the processor
associated with the other L2 caches in the system. The concern that
will be addressed here is the alternate way of handling cache misses
when the contention between processes involves data that is closely
shared.

      NECESSARY FEATURES AND DESIDERATA

      A process executing on a given processor-L1-cache may share
data with another process, and the mere sharing of a datum does not
mean that the totality of the investment that the process has made in
the L1 cache agrees with all the investment made by other processes
that wish to access that data.  The concept of interchanging
processors in order to reduce the impact of sharing is best addressed
at the L2 level which would permit the L1 caches to preserve their
process integrity despite the access rights to the data because of
the exclusive request by another processor.

      INTERCHANGING PROCESSORS AT THE TIME OF A CACHE MISS

      What we have called the ASYNCHRONOUS CACHE MISS involves the
decision made by the memory hierarchy to allow processes to exchange
processors at the time of a cache miss.  Involved in such a decision
and its implementation are three factors:
   The instruction (command) that would be issued by the memory
hierarchy that would effectuate such a switch including the saving of
all status.
   The implications on the memory hierarchy that would allow making
such a switching productive.
   A means of monitoring the degree of sharing on a given L2 so as to
determine for closely shared cache lines if a process-processor
switch is advantageous.

      EFFECTUATING A PROCESSOR SWITCH

      The instruction (command) that would be issued by the memory
hierarchy that would effectuate such a switch is not unlike the
software action taken in conjunction with an interrupt. All status
information about the processor must be saved and restored. Under
certain operating systems additional processor status is maintained
in a PREFIX STORAGE AREA (PSA). Also each processor is  assigned a
PROCESSOR ID (PROCID).  A special provision must be made to assure
that the PSAs of the two processors are exchanged, by the hardware,
and that the PROCIDs are reassigned so as to make the processor
switch transparent to the software. These additional aspects of
process-processor switching are potentially advantageous in other
contexts as well, such as enhancing reliability.

      THE IMPLICATIONS ON...