Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Single Transition Latch for Delay Testing

IP.com Disclosure Number: IPCOM000119873D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Vincent, BJ: AUTHOR

Abstract

By means of this level sensitive scan design (LSSD) latch circuit, timing, and application algorithm, AC performance of logic functions is tested.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 60% of the total text.

Single Transition Latch for Delay Testing

      By means of this level sensitive scan design (LSSD) latch
circuit, timing, and application algorithm, AC performance of logic
functions is tested.

      Signals to LSSD single transition latch (STL) (Fig. 1) are as
follows:
           A - Scan clock moves data on SI into L1
           SI- Scan in data from previous L2
           C - System clock moves data on D input into L1
           D - System data from logic or array
           B - Scan clock moves data from L1 to L2
           P - L3 clock moves data from L1 to L3
           T - Transition clock moves data on X into L1
           X - Final pattern data stored in L3
           SG- Scan gate for shift/parallel switch

      This circuit allows transformation of a DC stuck fault pattern
into an AC transition fault test pattern.  The timing diagram (Fig.
2) shows the function of cycles as follows:
           0 - Multicycles to load L3 with final pattern data
           1 - Multicycles to load L2 with initial pattern data
   2 - Switch from serial shift mode to parallel functional mode
   3 - Launch transitions and capture results with C clocks
           4 - Move captured data from L1 to L2
           5 - Switch from parallel to serial mode
           6 - Scan out test results
Note: Performance is measured by time interv...