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Patterning And Etching of Silicide Layers

IP.com Disclosure Number: IPCOM000119879D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

McFeely, FR: AUTHOR [+2]

Abstract

Silicide conductor layers are commonly used in silicon device technology, both for electrical contacts to silicon and for redistribution wiring. Complex processes are used to produce patterns of silicide conducting lines on the semiconductor chip. These processes usually involve numerous steps to carry out lithographic definition using resist layers, and then either wet or dry etching. In order to provide a more simple process, a single in-situ sequence of dry process steps is described for carrying out both the lithographic definition and the etching of the silicide conducting lines. A more controlled and reproducible process is obtained.

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Patterning And Etching of Silicide Layers

      Silicide conductor layers are commonly used in silicon
device technology, both for electrical contacts to silicon and for
redistribution wiring.  Complex processes are used to produce
patterns of silicide conducting lines on the semiconductor chip.
These processes usually involve numerous steps to carry out
lithographic definition using resist layers, and then either wet or
dry etching.  In order to provide a more simple process, a single
in-situ sequence of dry process steps is described for carrying out
both the lithographic definition and the etching of the silicide
conducting lines.  A more controlled and reproducible process is
obtained.

      Figs. 1-4 describe the process, which begins with a silicide
layer 10 located on a silicon substrate 12.  If the silicide layer 10
were annealed to temperatures above those normally required for
silicide compound formation, segregation of a silicon layer at the
top surface of the silicide 10 would result.  For the cases of Pd and
Pt, temperatures of 300-400 degrees C and 400-500 degrees C,
respectively, are sufficient to produce this Si overlayer.  This
technique also requires a source of the excess silicon, for instance,
a silicon substrate under the silicide layer 10 or excess Si in the
silicide layer.

      As shown in Fig. 2, patterning of a segregated silicon
overlayer is carried out by heating in a localized region by an
energy beam 14, which could be a las...