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Browse Prior Art Database

Four-Address Virtual Memory

IP.com Disclosure Number: IPCOM000119885D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 4 page(s) / 176K

Publishing Venue

IBM

Related People

Johnson, EE: AUTHOR

Abstract

This invention provides a virtual memory architecture for multiproces- sors which avoids TLB consistency problems under a wide range of sharing strategies, and allows pages of virtual memory objects to be mapped to any bank of physical memory.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 36% of the total text.

Four-Address Virtual Memory

      This invention provides a virtual memory architecture for
multiproces- sors which avoids TLB consistency problems under a wide
range of sharing strategies, and allows pages of virtual memory
objects to be mapped to any bank of physical memory.

      Four-address virtual memory provides a general framework for
accessing and managing virtual memory objects in multiprocessors.
Previous virtual memory architectures, when employed on
multiprocessors, have encountered problems in supporting common
strategies for sharing objects among processes running on several
processors,  maintaining processor TLB consistency without
significant performance loss, and/or retaining complete flexibility
in assigning (pages of) virtual memory objects to physical memory
banks. These problems are solved or avoided through the use of a
four-address virtual memory structure.

      The central concept of four-address virtual memory is to employ
a distinct type of address for each of the functions performed by
addresses in multiprocessors: process-specific and system-wide names
for objects, and the locations of pages in virtual and physical
memory. Processes directly generate process virtual addresses, whose
scope is limited to a single process; this permits the same process
virtual address to refer to different objects for different
processes.  Process virtual addresses are translated to unique object
addresses, which provide a name space of system-wide scope with
persistent mappings to objects (bound either for the lifetime of the
object, or for the entire period in which an object is mapped into
virtual memory).  Unique object addresses are, in turn, translated to
system virtual addresses which specify the locations in system
virtual memory of pages of virtual memory objects. Finally, system
virtual addresses are translated to physical addresses.

      An implementation of four-address virtual memory is shown in
the figure.  Such a virtual memory structure may be easily
implemented using current processors which support three-address
virtual memory (e.g., RISC System/6000*) by using the processors'
existing address translation facilities to perform the first two
translations (process virtual address to object address to system
virtual address), with the addresses produced at the pins of these
processors used as system virtual addresses rather than as physical
addresses.  Additional hardware is then required only to translate
these system virtual addresses to physical addresses.  To eliminate
translator consistency problems, as discussed below, this translation
is performed at the physical memory banks rather than at the
processors, with one address translator, or ATran, placed at each
memory bank.  Such global address translators add no more than one
clock period to global memory access time.

      System virtual memory (i.e., the system virtual address space)
is paged, rather than segmented-paged, to ma...