Browse Prior Art Database

Process Scheme to Make Shallow Trench Isolation Self-Aligned To the Storage Trench

IP.com Disclosure Number: IPCOM000119892D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 73K

Publishing Venue

IBM

Related People

Rajeevakumar, TV: AUTHOR

Abstract

For higher density DRAMs (256 Mb or higher per chip), the storage trench opening is small, the width being about 0.25 micron. The level-to-level alignment tolerance is about half this opening. As a result, a surface strap with sufficient contact area would require the isolation between the trenches (LOCOS or STI) be self-aligned to the storage trench. A process sequence is outlined below where the isolation between the trenches is made self-aligned to the trench. (1) First, the deep trench is etched, capacitor insulator is formed, and filled with poly and recessed, and oxide collar formed, as shown in Fig. 1. The silicon surface other than the trench is covered with pad oxide and silicon nitride.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 75% of the total text.

Process Scheme to Make Shallow Trench Isolation Self-Aligned To the
Storage Trench

      For higher density DRAMs (256 Mb or higher per chip), the
storage trench opening is small, the width being about 0.25 micron.
The level-to-level alignment tolerance is about half this opening.
As a result, a surface strap with sufficient contact area would
require the isolation between the trenches (LOCOS or STI) be
self-aligned to the storage trench.  A process sequence is outlined
below where the isolation between the trenches is made self-aligned
to the trench.
   (1) First, the deep trench is etched, capacitor insulator is
formed, and filled with poly and recessed, and oxide collar formed,
as shown in Fig. 1.  The silicon surface other than the trench is
covered with pad oxide and silicon nitride.
   (2) Silicon nitride is blanket deposited, followed by blanket
deposition of polysilicon and planarization using chemical mechanical
polishing.  The silicon nitride may be used as the polish stop.  The
polysilicon is now partially oxidized and planarized, as shown in
Fig.  2.
   (3) The isolation trench mask (IT) for the STI is now patterned.
Note that the isolation trench mask is designed to be inside the deep
trench by as much as one layer-to-layer alignment tolerance.  Using
the resist pattern, first the nitride is etched selectively to the
silicon, and then the silicon is etched selectively to the nitride
and oxide, as shown in Fig. 3.  The photoresist is now removed...