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Complementary Dual-Port Hazard-Free Polarity-Hold Latch

IP.com Disclosure Number: IPCOM000119911D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Banker, DC: AUTHOR [+3]

Abstract

Shown in Fig. 1 is a method of implementing a dual-port hazard-free polarity hold latch using both NPN and PNP transistors. The latch function that is implemented is: F = CF + CZD2 + CZD1 + FZD1 + FZD2 + CD1D2

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Complementary Dual-Port Hazard-Free Polarity-Hold Latch

      Shown in Fig. 1 is a method of implementing a dual-port
hazard-free polarity hold latch using both NPN and PNP transistors.
The latch function that is implemented is:
      F =  CF  +  CZD2  +  CZD1  +  FZD1  +  FZD2  +  CD1D2

      The functions FZD1, FZ-D2, and CD1D2 are redundant inputs which
are required to eliminate noise glitches caused by changing the gate
and data inputs.  The latch operates with a low voltage power supply
and uses a small signal swing.  The power dissipation is 10 W and the
performance is very fast.  A block diagram of the latch, shown in
Fig. 2, utilizes AND/OR logic.

      The z gate controls what data will be latched.  If the Z input
is at an "up" level, the clock will latch the D1 data.  If the Z
input is at a "down" level, the clock will latch the D2 data.  The
polarity of the data at the input to the latch will be maintained at
the output "F" for both D1 and D2 when the data is latched.