Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Le, TN: AUTHOR [+2]
Disclosed is an Expert System capable of generating any combination of functional test cases under user's direction to test the RISC System/6000* processor chip set logic design.
an Expert System capable of generating any
combination of functional test cases under user's direction to test
the RISC System/6000* processor chip set logic design.
consists of several steps. The first step
building a model which composes the real logic design files. Some
test case programs are then written to be run on this model via a
simulation utility. The results are compared to predicted results
(generated by another utility program or by the test case writer).
If the two sets of results do not match and the predicted results are
reasonably correct, the problem lies in the chip's logics.
(Architecture Verification Programs) and IVPs
(Implementation Verification Programs) are typically short programs.
AVPs and AVP-like IVPs (like AVPs but testing functions that compose
a specific sequence of instructions) are written with the RISC
System/6000 Assembly language instructions. The second component of
the IVPs is written in REXX, C, PL/8 or any other languages used in
the project. This component is to monitor the chip internal signals
and alter them in the hardware model to simulate errors during the
execution of the test case.
programs are to exercise certain functions specified in
the architecture (AVP) or functions not clearly specified in the
architecture but implemented in the logics (IVP).
expert system can generate any combination of