Browse Prior Art Database

Hierarchial Interconnection for Multiprocessors

IP.com Disclosure Number: IPCOM000119932D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 96K

Publishing Venue

IBM

Related People

Liu, L: AUTHOR

Abstract

Disclosed ia a technique for hierarchically interconnecting multiprocessors in order to reduce I/O pin requirement as storage controller.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Hierarchial Interconnection for Multiprocessors

      Disclosed ia a technique for hierarchically
interconnecting multiprocessors in order to reduce I/O pin
requirement as storage controller.

      Interconnection has been a critical issue in multiprocessor
designs.  In some multiprocessor systems, the processors are directly
connected to a storage controller. An example is the IBM 3090 system.
One problem in such approaches is the I/O pin requirement at the
storage controller, since it is fully connected to all the
processors.  Fig. 1 depicts a more general multiprocessor structure,
in which each of the N processors is directly connected to M separate
storage controllers (SCs).  An alternate to alleviate the I/O pin
burden at the storage controller(s) is to use hierarchical
interconnection.  Fig. 2 depicts such a structure, in which the
processor pair P2i and P2i+1 share buses to the two SCs via a
cross-point switch Si . With this design, the I/O requirement at the
SCs may be reduced significantly.

      In certain environments a straightforward implementation of the
structure in Fig. 2 may introduce new problems.  For instance, non-
existing switch components may be needed on the package.  One way of
eliminating such additional switch components is to build the
switches on the processor package units (e.g., modules).  Fig. 3
depicts such a realization for the structure of Fig. 2.  In Fig. 3,
each switch Si is split into two: S'2i and S'2i+1 .  Each S'j resides
on the package unit of Pj .  The processor pair P2i and P2i+1
connects to SCO (SC1, resp.)via the link between SCO (SC1, resp.) and
S'2i (S'2i+1, resp.). With such construction there will be additional
delays for some paths between processors and SCs.  For instance, P'1
needs to go through S'0 (on P0 package) in order to communicate with
SC0.  In certain designs, such additional delays will not cause
additional cycles for communication.  For instance, the exemplary
path between P1 and SC0 could be implemented as a typical single
cycle common bus (instead of a more conventional cross-point switch).
In certain other designs (especially when faster cycle times are
used), however, such additional delays may result in addi...