Browse Prior Art Database

Early Release of a Processor Following Address Translation Prior to Page Access Checking

IP.com Disclosure Number: IPCOM000119946D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 4 page(s) / 175K

Publishing Venue

IBM

Related People

Eberhard, RJ: AUTHOR

Abstract

Disclosed is a method for releasing a processor following virtual address translation prior to checking the page access key. This design provides a mechanism to track all references to a page of data within a checkpoint window so the S/370 page protection rules can be checked with a minimal amount of hardware and at maximal speed once a fetched access key is received from storage. This method will show that a significant amount of performance lost due to access key checking for virtual address translation in a processor can be recovered.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 38% of the total text.

Early Release of a Processor Following Address Translation Prior
to Page Access Checking

      Disclosed is a method for releasing a processor following
virtual address translation prior to checking the page access key.
This design provides a mechanism to track all references to a page of
data within a checkpoint window so the S/370 page protection rules
can be checked with a minimal amount of hardware and at maximal speed
once a fetched access key is received from storage.  This method will
show that a significant amount of performance lost due to access key
checking for virtual address translation in a processor can be
recovered.

      High performance processors use a Translation Lookaside Buffer
(TLB) to store the results of a virtual-to-real address translation
so a real page address can be quickly obtained when the page is next
referenced.  A real page address and its access key are stored
together in the TLB so the rules of page access can be checked when a
processor references a page.

      Although TLB misses are considered to be infrequent, the cost
in machine cycles to update a TLB with a translated address and page
access key is great.  The cycle penalty to perform this operation can
be in the order of thirty or more cycles.

      When examining the procedure used to update a TLB, a
significant performance penalty is incurred fetching the access key
that belongs to a translated 4k page.  This is because the access
keys are not stored in the processing unit since they need a large
amount of storage.  Also, a multiprocessor configuration requires
that they be located in hardware accessible by all the processors.

      Since a key request cannot be sent until the page address is
translated, the processor pipeline is stalled and the remainder of
the TLB update operation is spent waiting for an access key to be
returned from storage.  Once the access key is received, it is
checked according to the rules of page access and then stored in the
TLB along with the translated address.

      Key-controlled protection as well as the other forms of storage
protection are needed to protect storage from destruction by programs
that either contain errors or that are unauthorized [*].  Given that
key access exceptions rarely occur, a processor can be released
following address translation and prior to performing key-controlled
protection to regain several cycles previously lost to the key fetch.

      This proposal does not eliminate the need to check the access
key.  It suggests that the processor pipeline can be started along
with other processes while the access key is being fetched.  Also, an
additional virtual address is allowed to enter the translation
hardware when it would be otherwise idle.

      Following a storage reference that results in a TLB miss, an
absolute address will be calculated and then the processing unit will
be released.  Coincident with receiving the result of the absolute...