Browse Prior Art Database

RISC System/6000 Workstation Family Parity Error Text Fixture

IP.com Disclosure Number: IPCOM000119949D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Shempert, CH: AUTHOR [+2]

Abstract

The I/O architecture of the RISC System/6000* (hereinafter, RS/6000) has full address and data bus parity support for all adapter cards, internal cards and internal devices. All adapter cards to be supported for RS/6000 must provide parity generation and handling at the microchannel connector. Testing an adapter's implementation of this requirement is difficult, since these errors do not occur under normal, controlled conditions. Invasive circuit techniques to force an error by physically shorting a line results in machine state loss, since little control is possible over when and where the error is injected. In order to satisfy adapter architecture requirements, an AIX*-resident programmable and real-time test fixture method is indicated.

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This is the abbreviated version, containing approximately 100% of the total text.

RISC System/6000 Workstation Family Parity Error Text Fixture

      The I/O architecture of the RISC System/6000*
(hereinafter, RS/6000) has full address and data bus parity support
for all adapter cards, internal cards and internal devices.  All
adapter cards to be supported for RS/6000 must provide parity
generation and handling at the microchannel connector.  Testing an
adapter's implementation of this requirement is difficult, since
these errors do not occur under normal, controlled conditions.
Invasive circuit techniques to force an error by physically shorting
a line results in machine state loss, since little control is
possible over when and where the error is injected.  In order to
satisfy adapter architecture requirements, an AIX*-resident
programmable and real-time test fixture method is indicated.

      This solution, named PARCARD, occupies a location between the
host I/O bus and the adapter Card Under Test (CUT).  Full
programmable control through an AIX-resident device driver allows the
flexibility to inject several types of real-time errors to or from
the CUT while running normal applications or qualification test
units.  By means of bus monitoring of fixture and bus signal probe
points, Low End Parallel Bus Standard function and timing compliance
can be determined within a few minutes with pass/fail certainty.
*  Trademark of IBM Corp.