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Low Temperature Eutectic Solder Bump Process

IP.com Disclosure Number: IPCOM000119960D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 37K

Publishing Venue

IBM

Related People

Bergeron, R: AUTHOR [+5]

Abstract

To meet the ever growing requirements of mounting more chips in less card/board area, a unique low temperature eutectic solder bump ("E-Bump") process has been developed.

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This is the abbreviated version, containing approximately 85% of the total text.

Low Temperature Eutectic Solder Bump Process

      To meet the ever growing requirements of mounting more
chips in less card/board area, a unique low temperature eutectic
solder bump ("E-Bump") process has been developed.

      The E-Bump fabrication process begins post device/wafer
fabrication.  The wafer is precleaned via wet or dry processing
methods to remove native oxide and foreign material from the terminal
metal openings.  A controlled layer of Cr/Cu/Au is then evaporated
across the entire wafer surface.  Next, standard photolithographic
processing is used to define a resist image on top of the terminal
metal pads where the eutectic bump will eventually be formed.  The
Cr/Cu/Au is then etched using a combination of wet and reactive ion
etching (RIE) processes to remove the unwanted Cr/Cu/Au.  The resist
is then stripped.  Eutectic solder is then deposited on the terminals
by a molten solder application scheme.  Cross section micrographs of
the E-Bumps revealed positive wetting of solder with the terminals.
Using receptor pads on an organic carrier that are coated with
eutectic solder, low temperature joining of the chip to the carrier
may then be achieved using solder reflow.

      The advantages of the E-Bump process are: (1) no moly mask
required, (2) a well-controlled tin/lead eutectic bump is formed via
an inexpensive process, (3) the process is compatible with IBM as
well as vendor wafers, (4) method supplements solder volume
requirements f...