Browse Prior Art Database

High Temperature Logic Burn-In Screen

IP.com Disclosure Number: IPCOM000119965D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 30K

Publishing Venue

IBM

Related People

Abrami, AJ: AUTHOR

Abstract

The reliability effectiveness of any chip burn-in process is limited by time (tool capacity) and temperature (165 C). Disclosed is the use of a multipass, high temperature (200 degrees Celsius) multichip module burn-in methodology.

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High Temperature Logic Burn-In Screen

      The reliability effectiveness of any chip burn-in process
is limited by time (tool capacity) and temperature (165 C). Disclosed
is the use of a multipass, high temperature (200 degrees Celsius)
multichip module burn-in methodology.

      Chip reliability stress temperatures for non-sensitive circuit
families, usually VLSI logic, can approach 200 degrees Celsius.  The
increased temperature over prior use allows improved reliability for
equivalent tool hours or reduced burn-in tool requirements.  The
multipass methodology enables stress conditions, such as temperature
and voltage, to be varied on a per pass basis dependent on
differences in circuit families (bipolar, CMOS), circuit type (logic,
array) and module type.  For instance, a multichip module would be
populated with only logic chips, and the array chip sites would be
left blank or populated with terminator chips.  Temperature would be
ramped to 200 degrees Celsius, given the logic circuits to be
functional. The second pass would require population of the remaining
sites and a new set of stress conditions.  This multipass approach
can reduce chip failure rates as much as fifty percent over existing
one-pass reliability burn- in approaches.  In addition, it provides
the ability to tailor stress conditions per chip technology on the
same multichip carrier.