Browse Prior Art Database

New Process Method for Stacked Cells

IP.com Disclosure Number: IPCOM000119990D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 108K

Publishing Venue

IBM

Related People

Lu, NCC: AUTHOR

Abstract

A new processing method is described to implement stacked DRAM cell by epitaxy overgrowth technique, which allows using a higher isolation temperature without causing too much dopant diffusion.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

New Process Method for Stacked Cells

      A new processing method is described to implement stacked
DRAM cell by epitaxy overgrowth technique, which allows using a
higher isolation temperature without causing too much dopant
diffusion.

      A DRAM fabrication process for providing an epitaxial layer on
a silicon substrate and over predefined oxide-capped trench
capacitors which forms a self-aligned contact window in the epitaxial
layer is disclosed in [*]. The contact window is later filled with
silicon called a "neck" connection to the access device.  However, in
the proposed process steps, the device isolation is formed after both
the capped oxide inside the self-aligned window is removed and the
neck connection is formed.  Since the capped oxide is removed before
the isolation is formed, the dopants in the poysilicon inside the
trench can be out-diffused under the subsequent thermal cycles.  This
limits the temperature of forming isolation and may affect the device
short channel behavior.  As a result, a low temperature trench
isolation was proposed to be used in [*].

      This article describes a new processing method which allows
using a higher isolation temperature without causing too much dopant
diffusion.  The key process steps are described in the following:
 (1) Form the trench capacitor with capped oxide over the doped
polysilicon inside the trench, and the adjacent exposed silicon area
provides crystalline seeds for the epitaxy overgrowth.  By using
lateral epi overgrowth, a self-aligned contact area is formed (Fig.
1), just as the described in [*].
 (2) Then a thin pad oxide layer and a pad nitride layer are formed.
The pad nitride layer thickness is adjusted to overfill the contact
area (Fig. 2).  Continued masking and etching steps expose a silicon
area for the device isolation area.
 (3) Then the isolation region is formed, which can be thermal oxide
growth, such as ROX or shallow trench isolation, involving high
temperature steps (Fig. 3). Because the capped oxide over the trench
capacitor is not removed and protected by nitride and oxide, the
dopants in the polysilicon stay inside the trench.
 (4) Then another nitride layer is depo...