Browse Prior Art Database

Use of Facility Gate to Allow Direct Boolean Comparison of Clock Controls Along With Balance of Chip Logic

IP.com Disclosure Number: IPCOM000119991D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 134K

Publishing Venue

IBM

Related People

Schneiderman, A: AUTHOR

Abstract

High-level hardware description languages exist which are used as the source for the automatic generation of chip logic by means of a logic synthesis program. One such hardware description language consists of statements which may also be shown graphically as hardware flowcharts. After synthesis is done, designers may make logical changes to both the hardware flowchart description for the logic and logic itself. An independent means exists to verify that the logic and high-level flowchart description still are logically equivalent, without having to re-synthesize the entire design. This is done by a software system which performs Boolean Comparison by means of the Differential Boolean Analysis algorithm (*).

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Use of Facility Gate to Allow Direct Boolean Comparison of Clock
Controls Along With Balance of Chip Logic

      High-level hardware description languages exist which are
used as the source for the automatic generation of chip logic by
means of a logic synthesis program.  One such hardware description
language consists of statements which may also be shown graphically
as hardware flowcharts.  After synthesis is done, designers may make
logical changes to both the hardware flowchart description for the
logic and logic itself.  An independent means exists to verify that
the logic and high-level flowchart description still are logically
equivalent, without having to re-synthesize the entire design.  This
is done by a software system which performs Boolean Comparison by
means of the Differential Boolean Analysis algorithm (*).

      Problem: Typically, in a chip design, there is logic which is
used to control the gating of clocks so as to implement switching
from maintenance mode to scan mode to operational mode.  This logic
can be thought of as a set of cases wherein the clock to a latch
is gated by the output of another latch(es), or a chip primary input.
Such logic cannot now be Boolean Compared automatically along with
the other control and datapath logic without the use of techniques
requiring special cutouts and redefinition of clock nets.  The reason
for this is that hardware flowcharts only provide for one clock
source for a complete flowchart model.  Therefore, each latch in the
clock control logic and in the functional logic cannot be accurately
flowcharted to reflect the actual clocking conditions at the system
clock pin of the latches in the hardware, but instead must be
flowcharted in terms of the same clock variable SYSCLKB.

      Solution: The solution to the problem involves adding to
Boolean Comparison the availability of a feature now found in the
hardware Flowchart Simulator to allow the simulation of such clock
gating logic.  This feature is known as the "Facility Gate".  The
Facility Gate is a keyword on the Flowchart Simulator control
command, which controls the simulation of one or more files.  By
saying Facility Gate = CLK_STOP_ 1, latch assignments for the file
listed in the control statement are inhibited when CLK_STOP_1=1.  For
the purpose of this invention, each hardware flowchart file or set of
files could thus be specified with the appropriate Facility Gate
fac...