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Simpler And More Flexible Logic Design Through the Use of Mutually Referenced Current Switch Circuits

IP.com Disclosure Number: IPCOM000119999D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 7 page(s) / 195K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

This article illustrates the application of MRCS (Mutually Referenced Current Switch) circuits to Data Latch, J-K Flip-Flop, 2-Bit Carry and Full Adder design to improve performance, density, power and circuit count. Input signals are referenced to a shifted logic swing signal in each application.

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Simpler And More Flexible Logic Design Through the Use of Mutually
Referenced Current Switch Circuits

      This article illustrates the application of MRCS
(Mutually Referenced Current Switch) circuits to Data Latch, J-K
Flip-Flop, 2-Bit Carry and Full Adder design to improve performance,
density, power and circuit count.  Input signals are referenced to a
shifted logic swing signal in each application.

      Fig. 1 shows the commonly used gated data latch as configured
with MRCS.  It is assumed that the available input signals are the
T/C phases of the clock and the true phase of data at the elevated
swing levels.  Voltage levels of DD (input datum) and QQ (latched
datum) must be shifted above those of C and C by half a logic swing,
e.g., if C and C swing between -0.3 V and +0.3 V, then DD and
QQ should swing between 0.0 V and +0.6 V.  Exposure of the latch to
the occurrence of possible glitches common to conventional cascode
gated data latch design is prevented, as shown in Figs. 2 and 3, by
the addition of transistor 5.  In all cases the latch complement is
available at the collector of transistor 2.  While a single WRITE
port is implemented in the examples shown, extra ports can be added
by the extra sets of devices 1, 3, 4, 5 and Jd. DOWN levels of
QQ may need to be clamped, as shown in Figs. 2 and 3.

      MRCS circuits may also be employed to simplify the design of
the conventional J-K Flip-Flop, as shown in Fig. 4, in which the
input signals are referenced to each other. The logic representation
for this new J-K Flip-Flop, which is implemented with three simple
R/S (Reset/Set) latches, is shown in Fig. 5.  Each of these latches
appears as a 2-way NOR gate but functions as a Reset dominate R/S
latch.  Thus, they can be easily made from the common ECL gate array
books.  Circuit simplification is achieved by arranging the signals
J, K and L3 to swing at higher voltage levels.  For optimal noise
margins, these voltage levels are offset upward by half a logic swing
from the swing levels of the other signals, e.g., assume that Vcc =
1.4 V, Rs = 0.3 K, Rc = 0.6 K and Js + 1.0 mA,
then J, K and L3 swing between 0.0 V and +0.6 V, while all other
signals swing between -0.3 V and +0.3 V.  L1 is Reset dominate for
circuit simplicity, while L2 and L3 have to be Reset dominate for
functionality as well as for circuit simplicity.  When J and K are
high, L2 and L3 are forced to zeros so that L1 is undisturbed. The
Flip-Flop shown will also become a trigger Flip-Flop if J and K are
tied together.

      MRCS circuits in which input signals are referenced to a
shifted logic swing signal may also be applied to obtain improved
performance, density and power in the 2-bit carry computation.  Carry
is propagated upward along the tree in conventional CECL design to
the limit of cascode levels allowable in the technology.  This limit
can be extended by compressing cascode levels to allow for further
carry propagation within o...