Browse Prior Art Database

Comparator for Delay Regulator

IP.com Disclosure Number: IPCOM000120001D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Banker, DC: AUTHOR [+4]

Abstract

The function of the disclosed comparator is to compare two square waves labeled "Clock" and "Delayed Clock" and to indicate whether the "Delayed Clock" is arriving at, or later than, its expected time. It is assumed that the clock signal is a continuous square wave, and that the delayed clock delayed signal is formed by delaying the clock by half a cycle and inverting it as shown in Fig. 1.

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Comparator for Delay Regulator

      The function of the disclosed comparator is to compare
two square waves labeled "Clock" and "Delayed Clock" and to indicate
whether the "Delayed Clock" is arriving at, or later than, its
expected time.  It is assumed that the clock signal is a continuous
square wave, and that the delayed clock delayed signal is formed by
delaying the clock by half a cycle and inverting it as shown in Fig.
1.

      The wave forms shown in Fig. 1 illustrate a nominal delay
through the delay block.  Should the delay through the block be
longer than expected, the delayed clock signal would be shifted to
the right.  Conversely, if the delay is shorter than expected, the
delayed clock signal would be shifted to the left.

      The output of the comparator shown in Fig. 2 can be used to
enhance or diminish the delay of all logic circuits on a chip,
including the delay chain.  For example, if the delay is too short or
the circuits are too fast, the output of the comparator will provide
a "1" output.  If the delay is too long, i.e., the signal arrives too
late, a "0" output would be provided.  In this manner, the comparator
will continually cause the network to seek the nominal; never finding
it but oscillating around it, and thereby providing continuous
regulation of circuit performance on a chip.