Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Storing Into an MRU Cache

IP.com Disclosure Number: IPCOM000120018D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Ekanadham, K: AUTHOR [+3]

Abstract

In usual terms, the cache is considered to be: a set of congruence classes (CCs), each congruence class has a set associativity (SA), within each CC one of the lines is considered to be MRU.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Storing Into an MRU Cache

      In usual terms, the cache is considered to be:
        a set of congruence classes (CCs),
        each congruence class has a set associativity (SA),
        within each CC one of the lines is considered to be
        MRU.

      The ability of a cache to yield a one-cycle access to a
subclass of its lines, the lines that within each congruence class
are MRU, can be effectively made into the performance equivalent to
one cycle cache by certain processor organizational features one of
which is described herein.

      A distinction arises with respect to store operations in that
the store putaway is destructive and specific hardware is required to
restore the original contents of the cache if the MRU line is not the
target of the store.  This hardware can be dispensed with in the
event that it can be guaranteed that the putaway target is MRU and
early detection of the occurrence of a non-MRU store putaway target
is available.

      Consider the following three-stage pipeline in which the
instructions are denoted A, B, C, D, and E.  We image the pipeline
are deriving from the one-cycle cache.
                   STORE
                   PRETEST
        D/A  A B C D E
        C1         C
        EXEC         C
                       STORE
                       PUTAWAY

      In pipelined processors with a store-pretest, for each store
operation the action of the pretest will make the putaway MRU.  In
the above schematic, with instruction C being such a store, the
exposure to a loss of MRU status is only from instruction D.
However, in a general case, all succeeding instr...