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New Approach to the 'Window Method' for the Computation of Integrated Circuit Yield

IP.com Disclosure Number: IPCOM000120021D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 5 page(s) / 189K

Publishing Venue

IBM

Related People

Guedj, D: AUTHOR [+2]

Abstract

The IC yield is typically modeled with a negative binomial law (1). A common procedure to empirically obtain the 3 parameters Y0, a, g needed to fully describe this statistical distribution is given by Stapper (2) in the so-called 'window method'. In this approach, the average yield of virtual blocks of 1, 2, ..., n chips is plotted versus n, the number of chips per block. Fitting the experimental data with the expression Y = Y0 (1 + ng/ a) * -a yields the three unknowns.

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New Approach to the 'Window Method' for the Computation of Integrated
Circuit Yield

      The IC yield is typically modeled with a negative
binomial law (1). A common procedure to empirically obtain the 3
parameters Y0, a, g needed to fully describe this statistical
distribution is given by Stapper (2) in the so-called 'window
method'. In this  approach, the average yield of virtual blocks of 1,
2, ..., n chips is plotted versus n, the number of chips per block.
Fitting the experimental data with the expression  Y =  Y0 (1 + ng/
a) * -a yields the three unknowns.

      Stapper's method consists in grouping chips in non-overlapping
blocks. This is equivalent to making large chips on a wafer of
constant size. Several limitations can be seen:

      - As the block size is increased, the number of blocks
decreases.  This severely limits the precision of the data and,
therefore, the validity of the parameters obtained. In order to avoid
this problem, Stapper uses geometries that give the maximum number of
blocks for a given block size. Empirically, for typical chip and
wafer sizes, the maximum block size is limited by both the number of
possible blocks and the time it takes to define a good block mapping.
Refer to Table 1 to see that for a typical chip and wafer size, an
equivalent number of blocks can be achieved with blocks of 4 in the
old method and blocks of 12 in our approach. This gives a significant
improvement on the confidence we can have on the fitting parameters.
      block size      disjoint blocks     our approach
           1              124                 124
           2               60                 111
           3               35                  98
           4               27                  90
           5               19                  74
           6               15                  75
           7               13                  51
           8               11                  58
           9               10                  46
          10                9                  43
          11                6                  14
          12                5                  31
Table 1: Disjoint vs. overlapping blocks populations for a typical 1
cm2 chip placed on a 125 mm wafer
 - The block yield is strongly dependent on the way the blocks have
been defined (see numerical example). Several different geo metries
(e.g., horizontal, vertical...) need to be tested to obtain a
statistically meaningful...