Browse Prior Art Database

Hierarchical Neural Network-Based Controller for Crosspoint Networks

IP.com Disclosure Number: IPCOM000120025D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 4 page(s) / 163K

Publishing Venue

IBM

Related People

Varma, A: AUTHOR

Abstract

Disclosed is a two-level controller for real-time arbitration of switching paths in large crossbar switches constructed from one-sided crosspoint chips. The upper level uses a neural network for selection of the switching paths and the lower level is a conventional digital controller that performs the switching function by activating or deactivating the appropriate crosspoints.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 49% of the total text.

Hierarchical Neural Network-Based Controller for Crosspoint Networks

      Disclosed is a two-level controller for real-time
arbitration of switching paths in large crossbar switches constructed
from one-sided crosspoint chips.  The upper level uses a neural
network for selection of the switching paths and the lower level is a
conventional digital controller that performs the switching function
by activating or deactivating the appropriate crosspoints.

      Crossbar switches are used extensively as multiprocessor
interconnection networks and for communication switching.  A limiting
factor to the cost-effective single-chip realization of such large
arrays is the inductive noise generated by the line-drivers driving
the output leads of the chip.  When a large number of these drivers
are active simultaneously, a substantial transient current passes
through the inductance of the power distribution system, causing a
noise spike to emerge on the power lines.  This phenomenon is known
as the simultaneous switching noise or the Delta-I noise [1,2].  The
resulting fluctuation of the power-supply voltage level can cause
false switching of devices with an accompanying loss of data.

      The simultaneous-switching noise is particularly severe in
large crossbar switching chips because they have a large number of
data output lines.  This problem can be alleviated by constructing
crossbar networks using one-sided crosspoint switching chips (3).
Fig. 1 illustrates a one-sided crosspoint network with 32 ports
constructed from 8 x 4 chips.  These networks allow a pair of ports
to be connected using one of many available internal switching paths.
By choosing the switching paths properly, it is possible to
distribute the active off-chip drivers uniformly over the chip
matrix, thus reducing the Delta-I noise in each chip to acceptable
levels (4).

      In a non-blocking one-sided crossbar network, any request to
connect two idle ports can be satisfied without disturbing existing
connections.  However, when a constraint is placed on the allowable
number of concurrently-active line-drivers per chip, it is possible
that a connection-request is rejected even when a switching path is
available to connect them. Thus, the path allocation algorithm should
perform a joint optimization of network throughput and switching
noise.  In addition, the time taken to reconfigure the network should
be much smaller than the average duration of a connection request.
These objectives are met by a highly-parallel artificial
neural-network controller.

      The controller disclosed here is based on a two-level
architecture.  The top level consists of a neural network with one
neuron per crosspoint.   The bottom level is a conventional digital
controller that performs the actual reconfiguration by activating or
deactivating crosspoints. The controller allocates the active drivers
in the network so as to minimize the simultaneous-switching noise,
whi...