Browse Prior Art Database

Improved Bypass ECC

IP.com Disclosure Number: IPCOM000120026D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Aichelmann Jr, FJ: AUTHOR

Abstract

A method is proposed for providing a way to eliminate the time required for a correction cycle when a check bit is detected in error.

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This is the abbreviated version, containing approximately 100% of the total text.

Improved Bypass ECC

      A method is proposed for providing a way to eliminate the
time required for a correction cycle when a check bit is detected in
error.

      With conventional memory ECC implementations, the ECC facility
provides for a correction cycle for every correctable error.  This
proposal adds additional logic for evaluating whether the check bit
is the correctable error.  This evaluation circuit is then used as a
signal to the using system to bypass the correction cycle and take
the data.

      Fig. 1 depicts the block diagram of an ECC facility which has
an evaluator circuit included.  The evaluator circuit uses the
syndromes to detect when a check bit error occurs.  Fig. 2 shows an
example of the evaluation circuit for 8 check bits.  Fig. 3 is a flow
chart of a conventional ECC operations.  Fig. 4 describes the flow
chart modified for the improved bypass operations of this disclosure.