Browse Prior Art Database

Multiple Clock Checker

IP.com Disclosure Number: IPCOM000120029D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Aichelmann Jr, FJ: AUTHOR [+2]

Abstract

A method is proposed which provides checking of a multiple clock system within any time interval at the point of clock usage.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 83% of the total text.

Multiple Clock Checker

      A method is proposed which provides checking of a
multiple clock system within any time interval at the point of clock
usage.

      Increased emphasis on error reduction and error detection
requires that logic and clocking be checked at various points in the
propagation path.  Logic, using multiple clocks such as memory units
or cards, is sensitive to timing path errors at the point of clock
usage, which may be of some physical and logical distance from the
point of clock generation.  Clock errors which occur in a field
replaceable unit (FRU) in which the generation of these clocks is
contained may be very difficult to isolate.  The technique of clock
checking at the usage end of the path will assure maximum logic path
coverage and error isolation.

      Fig. 1 shows two decoders; one for all O's (down level), and
the other for all 1's (up level).  Fig. 2 shows how multiple clocks
may appear along with the decoder outputs and resultant pulse
generation from the toggled latch (pulses A, B, C and -).

      Clocks in high performance systems are generated to create 50%/
50% (up/down) or 40%/60% pulses to maintain pulse integrity clocks
overlap each other then in normal operation, thus providing some
point for coincidence of up and down lenses for decoder operation.
If failure of any one or several of these clocks occur, the set
and/or reset (A, B) cannot be generated.  The pulse detector (Fig. 1)
circuitry will detect that t...