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Self-Aligned FET With Gate-Drain Overlap Using a Disposable Pedestal

IP.com Disclosure Number: IPCOM000120032D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 106K

Publishing Venue

IBM

Related People

Gambino, JP: AUTHOR [+2]

Abstract

A number of gate-drain overlapped FET structures have been proposed (1,2,3) in order to achieve both high reliability and high performance. A lightly doped drain (LDD) is used to lower the drain electric field, resulting in less hot electron degradation (4). However, the LDD also increases the drain series resistance, which results in lower transconductance (4). By overlapping the gate with the LDD, the conductivity of the LDD is modulated by the gate voltage, resulting in a lower series resistance (1). In addition, the lateral electric field at the edge of the drain is reduced (more so than with the LDD alone) (1).

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Self-Aligned FET With Gate-Drain Overlap Using a Disposable Pedestal

      A number of gate-drain overlapped FET structures have
been proposed (1,2,3) in order to achieve both high reliability and
high performance.  A lightly doped drain (LDD) is used to lower the
drain electric field, resulting in less hot electron degradation (4).
However, the LDD also increases the drain series resistance, which
results in lower transconductance (4).  By overlapping the gate with
the LDD, the conductivity of the LDD is modulated by the gate
voltage, resulting in a lower series resistance (1).  In addition,
the lateral electric field at the edge of the drain is reduced (more
so than with the LDD alone) (1).

      In the previous proposals for gate-drain overlapped FETs, the
gate polysilicon in the overlap region was thinned using RIE with
either an oxide etch stop (1,2) or a timed etch (3).  The LDD was
implanted through the thinned region to create the overlap structure.
A disadvantage of the oxide etch-stop processes (1,2) is that the
electrical contact to the gate may be poor.  A disadvantage of the
timed etch process is that the gate polysilicon thickness in the
overlap region may vary, resulting in variations in the depth of the
LDD implant.

      In this disclosure, a process is described for fabricating
gate- drain overlapped FETs with good electrical contact to the gate
and good control of the gate polysilicon thickness in the overlap
region.  The process uses a disposable pedestal to mask the channel
during the LDD implant, and sidewalls along the pedestal to define
the gate and source/drain regions (see figures a-d).

      A possible process flow for an nFET is as follows:
a.   On a substrate with isolation and appropriate doping, thermally
grown, a gate oxide (100 Ao) and deposit thin polysilicon (1000 Ao).
The polysilicon must be thin enough so that the LDD can be implanted
through it. Dope the polysilicon during deposition, or with a doped
glass.  Note that implantation could also be used for nFETs, but
probably not for pFETs, because of B penetration through the gate
polysilicon during the implant. A thin Si02 (100 Ao) etch stop and a
Si3N4 pedestal 2000 o are deposited by CVD.  A resis...