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Partner Srls for Improved Shift Register Diagnostics

IP.com Disclosure Number: IPCOM000120037D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 5 page(s) / 160K

Publishing Venue

IBM

Related People

Policastri, FA: AUTHOR [+3]

Abstract

Shift Registers (SRs), present in LSSD (*) devices, are invaluable for the purpose of testing and diagnosing defects in the combinational logic that surrounds the shift register. However, a diagnostic quandary occurs when the SR itself is defective. This is mainly because the SR is only observable at the SR output, leaving no dependable method to identify which shift register latch (SRL) is faulty. Fault simulation, which is an extremely powerful tool for diagnosing combi- national faults, is very inefficient and ineffective for SR diagnostics. Almost all SR diagnostic tools today rely on direct SRL-to- primary output (PO) observability, which is not dependable since it limits I/O usage and is generally unacceptable to chip designers.

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Partner Srls for Improved Shift Register Diagnostics

      Shift Registers (SRs), present in LSSD (*) devices, are
invaluable for the purpose of testing and diagnosing defects in the
combinational logic that surrounds the shift register.  However, a
diagnostic quandary occurs when the SR itself is defective.  This is
mainly because the SR is only observable at the SR output, leaving no
dependable method to identify which shift register latch (SRL) is
faulty.  Fault simulation, which is an extremely powerful tool for
diagnosing combi- national faults, is very inefficient and
ineffective for SR diagnostics.  Almost all SR diagnostic tools today
rely on direct SRL-to- primary output (PO) observability, which is
not dependable since it limits I/O usage and is generally
unacceptable to chip designers.  As the density of LSSD devices
continues to increase, along with the length of SRs, this diagnostic
issue becomes a major problem that cannot be solved with fault
simulation or SRL-to-PO observability. Here, we introduce a SR
configuration that requires only a minimal amount of I/O and device
real estate, while yielding the ability to almost always diagnose a
defective SR to an SRL boundary.

      This invention describes a method of connecting a pair of shift
registers (of equal length) so that one SR can diagnose the other.
Fig. 1 shows two SRs, each having a length of four SRLs.  "Partner"
SRLs will be defined as two SRLs in different SRs having the same
position.  In this example, SRL #1 is the "partner" of SRL #2, and so
on.  Described in this article is a method to connect the output of
each SRL to the input of its "partner" SRL (Fig. 2).  The idea is for
the "good" SR to diagnose the "bad" SR down to an SRL boundary.

      Fig. 3 shows in detail how two partner SRLs can be connected.
The output of the L2 latch is wired to the SCAN input of the partner
L1, using a simple multiplexor (MUX). When in normal test mode, the
SELECT line will be turned off and the SCAN DATA is used as input to
the L1.  In "diagnostic" mode, however, the SELECT line would be
switched ON, thus allowing the output of the partner SRL to be
clocked into the L1 (by applying the 'A' scan clock). Therefore, the
"good" SR can capture the individual SRL values of the "bad" SR when
in diagnostic mode (SELECT line ON).

      Given this SR design, the defective SRL can be isolated by
applying some simple tests after the typical SR test (flush and
scan).  One example:
1.  SCANIN '111111....'into BOTH SRs.
2.  Turn SELECT line ON (diagnostic mode).
3.  Apply 'A' SCAN clock(s) to move L2 data to L1 in partner SRL.
4.  Turn SELECT line OFF.
5.  Apply 'B' SCAN clock to move data to L2.
6.  SCANOUT expected '111111....'of both SRs.
Then repeat the above with a scanin of '000000....'in step 1.
The remainder of the test would consist of the usual LSSD patterns
with the select line OFF.

      Consider, again, the example in Fig. 1, with two 4-bit...