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Logic Redundancy Cross Checking for Memory

IP.com Disclosure Number: IPCOM000120040D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Aichelmann Jr, FJ: AUTHOR

Abstract

A method is proposed for a logic redundancy structure which provides for a cross checking without requiring another element for detecting and comparing when faults occur. Additionally, this structure results in an on-line detection of faults, eliminating external intervention.

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This is the abbreviated version, containing approximately 100% of the total text.

Logic Redundancy Cross Checking for Memory

      A method is proposed for a logic redundancy structure
which provides for a cross checking without requiring another element
for detecting and comparing when faults occur. Additionally, this
structure results in an on-line detection of faults, eliminating
external intervention.

      With conventional logic redundancy implementations, an
additional element is required to determine which of the redundant
paths has a fault.  This proposal provides for a cross checking
between the two paths eliminating the need for an additional element
for detection and intervention.

      Fig. 1 depicts an error checking facility between interfaces.
This checking facility can be an element within a system that
incorporates error checking.  Fig. 2 shows a logic redundancy
structure for cross checking.  This structure incorporates two of the
error checking facilities of Fig. 1 into a cross- or self-checking
configuration which eliminates the need for an additional element for
intervention and detection.