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Bit-Line Current-Sensing Technique for CMOS Static RAM Cells

IP.com Disclosure Number: IPCOM000120056D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 50K

Publishing Venue

IBM

Related People

Dhong, SH: AUTHOR [+2]

Abstract

A new bit-line sensing technique for CMOS static RAM cells is disclosed. Essence of the new technique is to sense currents from a memory cell through a differential transresistance amplifier that converts the currents into voltage levels and to restore the bit lines at the logic threshold level of the memory cell. Read cycle time will improve because the bit-line swing is minimized for fast restoration. (Image Omitted)

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 59% of the total text.

Bit-Line Current-Sensing Technique for CMOS Static RAM Cells

      A new bit-line sensing technique for CMOS static RAM
cells is disclosed.  Essence of the new technique is to sense
currents from a memory cell through a differential transresistance
amplifier that converts the currents into voltage levels and to
restore the bit lines at the logic threshold level of the memory
cell.  Read cycle time will improve because the bit-line swing is
minimized for fast restoration.

                            (Image Omitted)

      The figure shows a CMOS implementation of the new
current-sensing technique for reading data stored in the static
memory cell (MOSFETs M1-M6).  The differential transresistance sense
amplifier (SA) consists of two CMOS differential amplifiers and
negative-feedback resistors (R1 and R2).  The resistors may be made
out of MOSFET or CMOS devices.  Bit-line precharge level is set at
the logic threshold of the cell and generated by shorting the two
storage nodes in a dummy cell.

      When the word-line (WL) level is low enough to turn off M5 and
M6, the bit-line currents are zero.  So if the sense amplifier is not
active (i.e., SELECT = '0'), the bit lines (BLT and BLC) are
precharged to the logic threshold.  If the sense amplifier is active
(i.e., SELECT = '1'), it operates as a unity-gain buffer, bringing
the bit- line voltages to the precharge level.

      When WL becomes active, assuming that the cell stor...