Browse Prior Art Database

Encapsulation Schemes for C4-Bonded Tab Packages

IP.com Disclosure Number: IPCOM000120063D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 105K

Publishing Venue

IBM

Related People

Ameen, JG: AUTHOR [+4]

Abstract

Disclosed is a method of encapsulating solder or aluminum bump bonded silicon chips to extremely low profile TAB (Tape Automated Bonded) thin film chip carriers which enhances the fatigue performance thereof.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Encapsulation Schemes for C4-Bonded Tab Packages

      Disclosed is a method of encapsulating solder or aluminum
bump bonded silicon chips to extremely low profile TAB (Tape
Automated Bonded) thin film chip carriers which enhances the fatigue
performance thereof.

      Bonding silicon devices to TAB thin film carriers is known in
the industry.  In a typical wire-bonding process, chip-joining is
normally done by thermo-compression bonding TAB wiring to silicon
chips.  Since the joints are susceptible to corrosion by chemicals
used in subsequent processes, they are protected with a low modulus
silicone gel as the encapsulant.  Although this process is feasible,
it is limited to small chips with low I/O count.  Since the
technology is heading for larger chips with denser I/Os, new
processes for chip joining, encapsulation materials and dispensing
techniques are being explored to meet these demands.

      Recent trends in TAB technology include the application of the
well-known flip-chip technology to such chip attachment.  Flip-chip
processing uses solder bump joining near the solder reflow
temperature.  The joints thus made are referred to as C4 (controlled
collapse chip connections) for simplicity.  Although the C4 joints
are highly reliable on thermally matched or low expansion chip
carriers (e.g., silicon, ceramics), these are vulnerable to fatigue
cracking during thermal excursions in the normal ATC (Accelerated
Thermal Cycling) testing.  The fatigue life is very sensitive to the
thermal expansion mismatch between the carrier and the chip, and the
distance from the neutral point (DNP).  Recently, it was found that
the C4 fatigue life can be enhanced by an order of magnitude by using
a low thermal expansion epoxy encapsulant covering the solder joints
(*).  The C4 life improvement is dramatically higher regardless of
substrate thermal expansion (CTE) as well as the DNP of the chip.  In
order to extend the flip-chip technology to TAB, it is crucial to
apply an epoxy encapsulant material to cover all the C4 joints.

      To get the best performance, it is highly desirable that the
epoxy possess a low CTE and high modulus prop...