Browse Prior Art Database

Combined Bus Master And Slave Redrive Circuits

IP.com Disclosure Number: IPCOM000120068D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 4 page(s) / 150K

Publishing Venue

IBM

Related People

Boldt, GD: AUTHOR [+3]

Abstract

The design described reduces the cost associated with using bipolar drivers as interface modules between FET (CMOS) logic devices and an external system bus. The design makes use of a single set of bidirectional bus drivers and appropriate controls to support both bus master, bus slave and mixed operating modes. This minimizes the number of redrive modules required. The use of the bidirectional redrive modules requires a complex set of controls to guarantee the correct sequencing of the CMOS and the redrive module drivers and receivers. It is essential that the switching of the devices from one mode to another be done without creating any driver conflicts or incorrect transitions (glitches) on the external bus.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Combined Bus Master And Slave Redrive Circuits

      The design described reduces the cost associated with
using bipolar drivers as interface modules between FET (CMOS) logic
devices and an external system bus.  The design makes use of a single
set of bidirectional bus drivers and appropriate controls to support
both bus master, bus slave and mixed operating modes.  This minimizes
the number of redrive modules required.  The use of the bidirectional
redrive modules requires a complex set of controls to guarantee the
correct sequencing of the CMOS and the redrive module drivers and
receivers.  It is essential that the switching of the devices from
one mode to another be done without creating any driver conflicts or
incorrect transitions (glitches) on the external bus.

      The figure illustrates the various possible operating modes and
corresponding driver conditions and control sequences.  There are
four sets of signals to be considered: the address lines, the data
lines, the bus master controls, and the bus slave controls.  The
figure shows the state of the CMOS and redrive module drivers and
receivers for these sets of signals for each of the possible bus
operations. For each bus operation, the control sequence to switch
the CMOS and redrive modules into the correct configuration and to
return to the default state are also shown.

      There are seven different bus operations that can be performed:
   1.   quiescent or default state (no activity on bus);
   2.   CMOS as a slave to another device (a write to the
        CMOS);
   3.   CMOS as a slave to another device (a read from the
        CMOS);
   4.   CMOS as a master (a write to another device);
   5.   CMOS as a master (a read from another device);
   6.   CMOS as a master and slave (a write from master to
        slave); and
   7.   CMOS as a master and slave (a read from slave to
        master).

      To operate correctly on the bus as a slave, the CMOS must
continuously monitor the bus for a memory select (MSEL) with the
correct address decodes.  Therefore, as a default state, the address
and master controls are directed in toward the CMOS.  The data lines
are disabled in both directions since the type of bus operation
cannot be predicted in advance.  The slave controls are...