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Mixed-Level Off-Chip Driver Circuit With Output Bus Pre-Charging Scheme

IP.com Disclosure Number: IPCOM000120071D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Katayama, Y: AUTHOR [+3]

Abstract

Disclosed is a circuit for a CMOS off-chip driver. An NMOS-only output stage can interface with an I/O node whose voltage becomes higher than the on-chip VDD. The pre-charging circuit achieves a high-speed and low-noise data transition on an output node, because the node is pre-charged to an intermediate voltage before data come, and swings from that voltage to VDD or VSS.

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Mixed-Level Off-Chip Driver Circuit With Output Bus Pre-Charging
Scheme

      Disclosed is a circuit for a CMOS off-chip driver.  An
NMOS-only output stage can interface with an I/O node whose voltage
becomes higher than the on-chip VDD.  The pre-charging circuit
achieves a high-speed and low-noise data transition on an output
node, because the node is pre-charged to an intermediate voltage
before data come, and swings from that voltage to VDD or VSS.

      Figs. 1 and 2 show the invented circuit and its simulated
waveform, respectively.  The circuit consists of an NMOS
boosting-capacitor TN1, an NMOS output-driver, and a pre-charging
circuit for the output node with a level-detection circuit. The
inputs are a data enable select (DES) and a pair of data bus (DB and
DBN). The output is OUT.

      Initially, the DES is high so that the output-driver and level-
detection circuit will be turned off.  The OUT maintains the high
impedance to the output node. Both DB and DBN are low.

      After DES becomes low, the pre-charging operation starts. When
OUT is to be driven low, TN5 is turned off and TP1 is turned on,
and N6 is connected with  DBN.  TN4 is turned off and TN2 is turned
on, which pre-charges  N5 to VDD - Vtn. Then TN7 pre-charges OUT to
VDD - 2 Vtn. When OUT is to be driven high, the level-detection
circuit pulls OUT down to  the switching point of NAND1. This
switching point is designed to be VDD - 2Vtn.

      When data arrive, either D...