Browse Prior Art Database

User-Defined Asynchronous Control of a Pattern Generator

IP.com Disclosure Number: IPCOM000120086D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 83K

Publishing Venue

IBM

Related People

Henderson, DJ: AUTHOR [+2]

Abstract

Disclosed is a pattern generator device controlled by user-defined asynchronous logic rather than fixed random or programmed synchronous logic (*). The device permits logic emulation of interfaces using a pattern generator approach for emulation of signals, but allowing the state transitions to occur based on user-defined asynchronous events including response to asynchronous events from the interface being emulated.

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User-Defined Asynchronous Control of a Pattern Generator

      Disclosed is a pattern generator device controlled by
user-defined asynchronous logic rather than fixed random or
programmed synchronous logic (*).  The device permits logic emulation
of interfaces using a pattern generator approach for emulation of
signals, but allowing the state transitions to occur based on
user-defined asynchronous events including response to asynchronous
events from the interface being emulated.

      The asynchronous logic controller and the pattern generator are
implemented using RAM based devices which can be programmed from a
host without the need to change physical hardware.

      The device in adapter card form is shown in the figure. The
major parts of the device are:
EXTERNAL COMMUNICATIONS CHANNEL AND CONTROL LOGIC:

      The External Communications Channel and Control Logic consists
of a microprocessor and a communications interface, such as the
IEEE-488 interface.  The microprocessor controls the configuration of
and access to facilities on the card and communication with the
external environment via the communications interface.
ASYNCHRONOUS CONTROLLER:

      The Asynchronous Controller consists of a small amount of RAM
and user-definable sequencer and controller.  The sequencer is
implemented using Programmable Gate Arrays known as Logic Cell
Arrays* or LCAs*.  These LCAs contain both combinatorial logic and
latches whose functions and interconnections are determined by
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