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Semiconductor Chip I/O Configuration for Plastic Flat Pack, Tape Automated Bonding, Or Solder Ball Joined Flip Chip Packages

IP.com Disclosure Number: IPCOM000120103D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Gow, J: AUTHOR [+2]

Abstract

A CMOS chip I/O design is shown which allows for either plastic flat pack (PFP), tape automated bonding (TAB), or solder ball joined flip chip packages, thus eliminating the need for separate chip designs.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 80% of the total text.

Semiconductor Chip I/O Configuration for Plastic Flat Pack, Tape
Automated Bonding, Or Solder Ball Joined Flip Chip Packages

      A CMOS chip I/O design is shown which allows for either
plastic flat pack (PFP), tape automated bonding (TAB), or solder ball
joined flip chip packages, thus eliminating the need for separate
chip designs.

      With the continued integration of CMOS logic chips, improved
chip I/O to packaging density, as well as increased packaging I/O
capability, is required. By utilizing the current manufacturing
process for CMOS chips, there are two key limitations which establish
how closely the chip I/Os can be placed, namely:
1. The capability of the chip I/O pad spacing process.
2. The test probe capability at a wafer level.

      Consistent with the state of the art using 4 mil pads, the
following minimum pitch dimensions apply:
1. Minimum PFP (wire bond) pitch is 6 mils.
2. Minimum test probe pitch is 9 mils.
3. Minimum solder ball connection pitch is 10 mils.

      The wire bond structures maintain in-line pads and a constant
100 mil wire length for single pass high productivity. TAB and solder
ball connected chips are not restricted to in-line pads and may use
staggered I/O pads. Referring to the figure, a staggered I/O pad
layout is shown which accommodates multiple chip I/O designs where
lead transparency eliminates the need for separate chip I/O designs.

      TAB module structures offer a performance improvement over PFP
m...