Browse Prior Art Database

Compounding Instructions in the Execution Unit

IP.com Disclosure Number: IPCOM000120105D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 92K

Publishing Venue

IBM

Related People

Rechtschaffen, RN: AUTHOR [+3]

Abstract

In usual terms, the cache is considered to be: a set of congruence classes (CC), each congruence class has a set associativity (SA), within each CC one of the lines is considered to be MRU.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Compounding Instructions in the Execution Unit

      In usual terms, the cache is considered to be:
    a set of congruence classes (CC),
    each congruence class has a set associativity (SA),
    within each CC one of the lines is considered to be MRU.

      The ability of a cache to yield a one-cycle access to a
subclass of its lines, the lines that within each congruence class
are MRU, can be effectively made into the performance equivalent to
one-cycle cache by certain processor organizational features one of
which is described herein.

      To understand this aspect one must have a firm grasp on the
processor organization. To this end, the invention will be described
in the context of an IBM 3033 organization although it applies to a
much broader organization. The distinction from the IBM 3033
organization will be in the following four areas:
    A SPLIT I/D CACHE
    AN E_SETUP_TIME OF 1 FOR ALL INSTRUCTIONS
    A SINGLE CYCLE MRU ACCESS CACHE
    COMPOUNDING IN THE E-UNIT

      The reduction in C/I based on a one-cycle cache access comes
almost entirely from the similar reduction in ENBZY. This reduction
can further be quantified as relating to a reduction in:
1.  AGI DELAY
     a.  AGIM
     b.  AGIL  *
2.  BRANCH DELAY
     a.  BRANCH RESOLUTION TIME  *
     b.  FETCHING THE BRANCH TARGET
3.  DISABLE OVERLAP AND SERIALIZERS
     a.  PIPELINE DRAIN  *
     b.  REFETCHING THE I-BUFFER

      The asterisked items reflect the improvement potential
associated with E-UNIT COMPOUNDING to restore E_SETUP_TIME of the
shorter pipeline.

      Within the standard D/A - C1 - E and D/A - C1 - C2
- E pipeline alternatives, the action of compounding is performed
during the C1 cycle of the instruction because the pipeline status of
the previous instruction is then known. The ability to compound any
two instructions depends on the execution unit and register bandwidth
within the processor. The aspect of compounding will, when
successful, restore the pipeline to the morphology of the shorter
pipeline without executing instructions out of their original
sequence.

      A more general application of compounding at different stages
of the pipeline is presented below. Again, the simultaneity of the
compounding cleverly sidesteps the issue of out-of-sequence so that
the usual caveats need not become a concern. This relates...