Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Hierarchical Probing of Transparent Hardware Features: Register Renaming

IP.com Disclosure Number: IPCOM000120109D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 125K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

The testing and detection of transparent features in a processor design is ultimately a performance question. The question, "does it work?", is more than the issue of not producing erroneous results. The question here is a performance issue. Most broadly, all performance features that are transparent to the code being executed, such as pipelining, cache, handling of instruction buffers, and the newer features, such as BHT, register renaming, out-of-sequence execution, multiple decodes per cycle, all must be tested for their performance in synthetic situations to assure that they are operationally correct. TESTING A PROCESSOR DESIGN

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 48% of the total text.

Hierarchical Probing of Transparent Hardware Features: Register Renaming

      The testing and detection of transparent features in a
processor design is ultimately a performance question. The question,
"does it work?", is more than the issue of not producing erroneous
results. The question here is a performance issue.  Most broadly, all
performance features that are transparent to the code being executed,
such as pipelining, cache, handling of instruction buffers, and the
newer features, such as BHT, register renaming, out-of-sequence
execution, multiple decodes per cycle, all must be tested for their
performance in synthetic situations to assure that they are
operationally correct.
TESTING A PROCESSOR DESIGN

      For most operations within a machine a simple test with an
elaborate set of options is sufficient to guarantee that all
instances of the instruction that occur in any possible context will
perform correctly. An example of a simple test is repeated executions
of the same instruction.  This has the danger of creating performance
estimates for instructions that combine execution timings with cache
bandwidth limitations and overly penalizing the instructions which
access memory for their operands. Overestimates for STORE type
instructions and LOAD type instructions are common in such tests.
Further, for a class of operations which have a strong contextual
aspect this simplicity of the test is absent.

      The defining characteristic of the features of the processor is
that they have a strong contextual aspect. Beyond this aspect is an
additional aspect associated with a memory which may alter the
dynamically adjustable aspects of the design so as to have
performance implications many cycles later. Those features that have
a memory have to be tested for two facets: their existence and the
size of their memory. The features that do not have a memory or the
existence of features that do have a memory can be tested with short
instruction sequences as their impact is felt within a few cycles if
a needed resource is delayed. Among such features with a memory are:
    CACHE
    BHT
and features that do not have a memory are:
    OUT-OF-SEQUENCE EXECUTION
    REGISTER RENAMING.

      The basic questions that will be addressed are:
   What distinguishes these features?
   How should these features be tested?
   How should these features be evaluated?

      The test approach that shall be proposed is called the NULL
TEST.  The point of view that can be pursued is to design a specific
code sequence which, when varied appropriately, can show performance
differences in the presence of certain design features. Further, the
anticipated performance of such code or some singular expected result
can test the feature within the processor and, more hopefully, within
the design at an earlier stage. That is, what program sequence can
detect if the processor does register renaming, and does it do it as
to speci...