Browse Prior Art Database

Shielding Technique Through Card And Rack Connections

IP.com Disclosure Number: IPCOM000120110D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Murphy, DJ: AUTHOR

Abstract

By using a printed circuit (PC) board having a minimum of three layers for card and rack circuits and shielding, the shielding (G) around power (P) and/or output signal (S) lines may be maintained at the same potential as the P and/or the S lines, thereby avoiding generation of current by parasitic resistance. Leakage current generated by, e.g., wire wrap pins protruding from a card rack, is also avoided by this shielding technique.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 89% of the total text.

Shielding Technique Through Card And Rack Connections

      By using a printed circuit (PC) board having a minimum of
three layers for card and rack circuits and shielding, the shielding
(G) around power (P) and/or output signal (S) lines may be maintained
at the same potential as the P and/or the S lines, thereby avoiding
generation of current by parasitic resistance.  Leakage current
generated by, e.g., wire wrap pins protruding from a card rack, is
also avoided by this shielding technique.

      The figures illustrate the technique by showing only a power
bus P and shielding G.  Referring to Fig. 1, backplane 10 is shown
having three wire wrap pins 12 protruding from its back.  Two of pins
12 are shielding G for power pin P.  Pins 12 connect to bent pins 14
from card 16 via connector 18.  Conductors in backplane 10 and card
16 are not shown in Fig. 1.

      Referring to Fig. 2, configuration and connections of
conductors in PC boards 10 and 16 of Fig. 1 to shielding G and bus
P are shown as three insulating layers 20, 22, and 24 having only
continuous shielding conductors G on layers 20 and 24.  Power bus P
on layer 22 has shielding wires G running parallel on both sides.

      Fig. 3 shows a plan view of the conductor patterns on each of
the three layers 20, 22 and 24 in the vicinity of connector pins 12
or 14 in PC boards 10 and 16.  Layers 20 and 24 have their shielding
conductors connected to at least three shielding pins G to surround
power...