Browse Prior Art Database

Global Process for Mapping Non-LSSD Logic to LSSD Logic

IP.com Disclosure Number: IPCOM000120118D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Chiriatti, LL: AUTHOR

Abstract

The process consists of adding inputs to non-Level-Sensitive Scan Design (LSSD) latches similar to those found in LSSD testable structures and then replacing the non-LSSD latches with these modified, more testable equivalents. The revised circuits are connected to allow multiple clocks to control testing through LSSD means. Significant increase in testability is achieved by this global change to the testing structure of logic even when there is minimal knowledge of an original logic design.

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Global Process for Mapping Non-LSSD Logic to LSSD Logic

      The process consists of adding inputs to
non-Level-Sensitive Scan Design (LSSD) latches similar to those found
in LSSD testable structures and then replacing the non-LSSD latches
with these modified, more testable equivalents.  The revised circuits
are connected to allow multiple clocks to control testing through
LSSD means.  Significant increase in testability is achieved by this
global change to the testing structure of logic even when there is
minimal knowledge of an original logic design.

      Referring to Fig. 1, typical non-LSSD latch 10 has inputs:
system clock C and clear R; and positive and negative outputs +Q and
-Q.  By adding scan input T0, test input T1, test reset TR, scan
clock A0, test clock B, and scan input I0 to all latches in a system,
the latches become LSSD testable.  At this stage of the mapping
procedure, common inputs to all chip logical boundaries are connected
together, e.g., all A0s are connected together, all T0s are connected
together, etc.  A standard circuit design editing program is used to
create necessary inputs to the latches.

      Each latch type is replaced by its LSSD equivalent expansion
model as represented in Fig. 2.  Non-LSSD latch 10 of Fig. 1 is
replaced by scannable latch 12 plus the addition of control logic
(inverters I, ORs O, and ANDs A) as shown.  Any of several expansion
software tools may be used to perform this transformation.

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