Browse Prior Art Database

SCSI Initiator Skip Read Write Implementation

IP.com Disclosure Number: IPCOM000120127D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 6 page(s) / 173K

Publishing Venue

IBM

Related People

Bakke, BE: AUTHOR [+2]

Abstract

A method for implementing the Skip Read and Skip Write functions in a Small Computer System Interface (SCSI) Initiator is disclosed. This method does not require any microprocessor interrupts between either the Load Skip Mask Read/Read Extended linked command pair or the Load Skip Mask Write/Write Extended linked command pair. Also, each linked command pair requires only a single DMA channel.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

SCSI Initiator Skip Read Write Implementation

      A method for implementing the Skip Read and Skip Write
functions in a Small Computer System Interface (SCSI) Initiator is
disclosed.  This method does not require any microprocessor
interrupts between either the Load Skip Mask Read/Read Extended
linked command pair or the Load Skip Mask Write/Write Extended linked
command pair.  Also, each linked command pair requires only a single
DMA channel.

      An I/O Processor is partitioned as shown in Fig. 1. The System
Adapter performs the system DMA controller function.  The SCSI DMA
controller (SDCA) performs the SCSI I/O path control function.  The
Mag Media Bus transfers data in a streaming byte mode between DMA
paths in the System Adapter and the SDCA.

      The SDCA addresses the DASD in Logical Blocks.  Each Logical
Block is 520 bytes, 8 bytes of system information or Header followed
by 512 bytes of Data.  System main storage is divided into 512 byte
pages.  A page contains either 512 bytes of data or 1 to 64 8 byte
headers.

      SKIP WRITE SEQUENCE

      The Skip Write sequence consists of the following steps:
1.   Parameter setup (see "Skip Write Setup")
2.   Execution (see "Skip Write Execution")
3.   Command post processing

      SKIP WRITE SETUP:  The microcontroller loads the parameters
shown in Table 1 (Fig. 2) into the SDCA Path Control registers and
Buffer RAM.

      SKIP WRITE EXECUTION:  Refer to Fig. 3.
1.   The SDCA selects the DASD and transfers the command bytes
starting at offset zero in the command buffer.
2.   The DASD proceeds to data phase to request the Skip Mask.  The
Transfer Mode Register is set to inhibit header separation and there
is a non-zero header byte count so the SDCA proceeds to Acknowledge
the DASD Requests by sending data from the header buffer.
3.   The DASD will send an Intermediate Good status byte and a Linked
Command Complete Message.  Once this message is received, the Linked
Transfer Mode Register overlays the Mode Register.  The DASD goes to
command phase. The SDCA transfers the command bytes starting at
offset sixteen in the command buffer.
4.   The Mag Media bus fills the Header Buffer until the Header Byte
Count equals zero.
5.   The Mag Media bus fills the Data Buffer.
...